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drm/rockchip: vop: sync with linux-4.19 for rk3399 vop

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Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I7f703780d86ee964051a3ad2896745b34e852ccb
This commit is contained in:
Sandy Huang
2021-09-02 09:30:02 +08:00
committed by Tao Huang
parent bcbc992aaa
commit fa6c7f1111
5 changed files with 5419 additions and 1955 deletions
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7
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View File

@@ -157,6 +157,11 @@ struct rockchip_crtc_funcs {
void (*crtc_send_mcu_cmd)(struct drm_crtc *crtc, u32 type, u32 value); void (*crtc_send_mcu_cmd)(struct drm_crtc *crtc, u32 type, u32 value);
}; };
struct rockchip_dclk_pll {
struct clk *pll;
unsigned int use_count;
};
/* /*
* Rockchip drm private structure. * Rockchip drm private structure.
* *
@@ -187,6 +192,8 @@ struct rockchip_drm_private {
const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC]; const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC];
struct rockchip_dclk_pll default_pll;
struct rockchip_dclk_pll hdmi_pll;
struct rockchip_drm_vcnt vcnt[ROCKCHIP_MAX_CRTC]; struct rockchip_drm_vcnt vcnt[ROCKCHIP_MAX_CRTC];
/** /**
* @loader_protect * @loader_protect

4370
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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File diff suppressed because it is too large Load Diff

572
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -18,10 +18,13 @@
#define VOP_MAJOR(version) ((version) >> 8) #define VOP_MAJOR(version) ((version) >> 8)
#define VOP_MINOR(version) ((version) & 0xff) #define VOP_MINOR(version) ((version) & 0xff)
#define VOP2_SOC_VARIANT 4 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
#define NUM_YUV2YUV_COEFFICIENTS 12 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
#define AFBDC_FMT_RGB565 0x0
#define AFBDC_FMT_U8U8U8U8 0x5
#define AFBDC_FMT_U8U8U8 0x4
#define VOP_FEATURE_OUTPUT_10BIT BIT(0) #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
#define VOP_FEATURE_AFBDC BIT(1) #define VOP_FEATURE_AFBDC BIT(1)
#define VOP_FEATURE_ALPHA_SCALE BIT(2) #define VOP_FEATURE_ALPHA_SCALE BIT(2)
@@ -43,53 +46,7 @@
#define WIN_FEATURE_MULTI_AREA BIT(7) #define WIN_FEATURE_MULTI_AREA BIT(7)
#define DSP_BG_SWAP 0x1 #define VOP2_SOC_VARIANT 4
#define DSP_RB_SWAP 0x2
#define DSP_RG_SWAP 0x4
#define DSP_DELTA_SWAP 0x8
/* AFBC supports a number of configurable modes. Relevant to us is block size
* (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like
* colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode
* could be enabled via the hreg_block_split register, but is not currently
* handled. The colourspace transform is implicitly always assumed by the
* decoder, so consumers must use this transform as well.
*
* Failure to match modifiers will cause errors displaying AFBC buffers
* produced by conformant AFBC producers, including Mesa.
*/
#define ROCKCHIP_AFBC_MOD \
DRM_FORMAT_MOD_ARM_AFBC( \
AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \
| AFBC_FORMAT_MOD_YTR \
)
enum vop_data_format {
VOP_FMT_ARGB8888 = 0,
VOP_FMT_RGB888,
VOP_FMT_RGB565,
VOP_FMT_YUV420SP = 4,
VOP_FMT_YUV422SP,
VOP_FMT_YUV444SP,
};
enum _vop_sdr2hdr_func {
SDR2HDR_FOR_BT2020,
SDR2HDR_FOR_HDR,
SDR2HDR_FOR_HLG_HDR,
};
enum _vop_rgb2rgb_conv_mode {
BT709_TO_BT2020,
BT2020_TO_BT709,
};
enum vop_csc_format {
CSC_BT601L,
CSC_BT709L,
CSC_BT601F,
CSC_BT2020,
};
enum bcsh_out_mode { enum bcsh_out_mode {
BCSH_OUT_MODE_BLACK, BCSH_OUT_MODE_BLACK,
@@ -98,6 +55,17 @@ enum bcsh_out_mode {
BCSH_OUT_MODE_NORMAL_VIDEO, BCSH_OUT_MODE_NORMAL_VIDEO,
}; };
enum cabc_stage_mode {
LAST_FRAME_PWM_VAL = 0x0,
CUR_FRAME_PWM_VAL = 0x1,
STAGE_BY_STAGE = 0x2
};
enum cabc_stage_up_mode {
MUL_MODE,
ADD_MODE,
};
/* /*
* the delay number of a window in different mode. * the delay number of a window in different mode.
*/ */
@@ -108,128 +76,216 @@ enum vop2_win_dly_mode {
VOP2_DLY_MODE_MAX, VOP2_DLY_MODE_MAX,
}; };
#define DSP_BG_SWAP 0x1
#define DSP_RB_SWAP 0x2
#define DSP_RG_SWAP 0x4
#define DSP_DELTA_SWAP 0x8
enum vop_csc_format {
CSC_BT601L,
CSC_BT709L,
CSC_BT601F,
CSC_BT2020,
};
enum vop_csc_mode {
CSC_RGB,
CSC_YUV,
};
enum vop_data_format {
VOP_FMT_ARGB8888 = 0,
VOP_FMT_RGB888,
VOP_FMT_RGB565 = 2,
VOP_FMT_YUYV = 2,
VOP_FMT_YUV420SP = 4,
VOP_FMT_YUV422SP,
VOP_FMT_YUV444SP,
};
struct vop_reg_data {
uint32_t offset;
uint32_t value;
};
struct vop_reg {
uint32_t mask;
uint32_t offset:17;
uint32_t shift:5;
uint32_t begin_minor:4;
uint32_t end_minor:4;
uint32_t reserved:2;
uint32_t major:3;
uint32_t write_mask:1;
};
struct vop_csc {
struct vop_reg y2r_en;
struct vop_reg r2r_en;
struct vop_reg r2y_en;
struct vop_reg csc_mode;
uint32_t y2r_offset;
uint32_t r2r_offset;
uint32_t r2y_offset;
};
struct vop_rect { struct vop_rect {
int width; int width;
int height; int height;
}; };
struct vop_hdr_table { struct vop_ctrl {
const uint32_t hdr2sdr_eetf_oetf_y0_offset; struct vop_reg version;
const uint32_t hdr2sdr_eetf_oetf_y1_offset; struct vop_reg standby;
const uint32_t *hdr2sdr_eetf_yn; struct vop_reg dma_stop;
const uint32_t *hdr2sdr_bt1886oetf_yn; struct vop_reg axi_outstanding_max_num;
const uint32_t hdr2sdr_sat_y0_offset; struct vop_reg axi_max_outstanding_en;
const uint32_t hdr2sdr_sat_y1_offset;
const uint32_t *hdr2sdr_sat_yn;
const uint32_t hdr2sdr_src_range_min;
const uint32_t hdr2sdr_src_range_max;
const uint32_t hdr2sdr_normfaceetf;
const uint32_t hdr2sdr_dst_range_min;
const uint32_t hdr2sdr_dst_range_max;
const uint32_t hdr2sdr_normfacgamma;
const uint32_t sdr2hdr_eotf_oetf_y0_offset;
const uint32_t sdr2hdr_eotf_oetf_y1_offset;
const uint32_t *sdr2hdr_bt1886eotf_yn_for_hlg_hdr;
const uint32_t *sdr2hdr_bt1886eotf_yn_for_bt2020;
const uint32_t *sdr2hdr_bt1886eotf_yn_for_hdr;
const uint32_t *sdr2hdr_st2084oetf_yn_for_hlg_hdr;
const uint32_t *sdr2hdr_st2084oetf_yn_for_bt2020;
const uint32_t *sdr2hdr_st2084oetf_yn_for_hdr;
const uint32_t sdr2hdr_oetf_dx_dxpow1_offset;
const uint32_t *sdr2hdr_st2084oetf_dxn_pow2;
const uint32_t *sdr2hdr_st2084oetf_dxn;
const uint32_t sdr2hdr_oetf_xn1_offset;
const uint32_t *sdr2hdr_st2084oetf_xn;
};
struct vop_reg {
uint32_t mask;
uint16_t offset;
uint8_t shift;
bool write_mask;
bool relaxed;
};
struct vop_afbc {
struct vop_reg enable;
struct vop_reg win_sel;
struct vop_reg format;
struct vop_reg hreg_block_split;
struct vop_reg rb_swap;
struct vop_reg uv_swap;
struct vop_reg auto_gating_en;
struct vop_reg rotate;
struct vop_reg block_split_en;
struct vop_reg pic_vir_width;
struct vop_reg tile_num;
struct vop_reg pic_offset;
struct vop_reg pic_size;
struct vop_reg dsp_offset;
struct vop_reg transform_offset;
struct vop_reg hdr_ptr;
struct vop_reg half_block_en;
struct vop_reg xmirror;
struct vop_reg ymirror;
struct vop_reg rotate_270;
struct vop_reg rotate_90;
struct vop_reg rstn;
};
struct vop_modeset {
struct vop_reg htotal_pw; struct vop_reg htotal_pw;
struct vop_reg hact_st_end; struct vop_reg hact_st_end;
struct vop_reg hpost_st_end;
struct vop_reg vtotal_pw; struct vop_reg vtotal_pw;
struct vop_reg vact_st_end; struct vop_reg vact_st_end;
struct vop_reg vact_st_end_f1;
struct vop_reg vs_st_end_f1;
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end; struct vop_reg vpost_st_end;
}; struct vop_reg vpost_st_end_f1;
struct vop_reg post_scl_factor;
struct vop_output { struct vop_reg post_scl_ctrl;
struct vop_reg pin_pol; struct vop_reg dsp_interlace;
struct vop_reg dp_pin_pol; struct vop_reg global_regdone_en;
struct vop_reg dp_dclk_pol; struct vop_reg auto_gate_en;
struct vop_reg edp_pin_pol; struct vop_reg post_lb_mode;
struct vop_reg edp_dclk_pol; struct vop_reg dsp_layer_sel;
struct vop_reg hdmi_pin_pol; struct vop_reg overlay_mode;
struct vop_reg hdmi_dclk_pol; struct vop_reg core_dclk_div;
struct vop_reg mipi_pin_pol; struct vop_reg dclk_ddr;
struct vop_reg mipi_dclk_pol; struct vop_reg p2i_en;
struct vop_reg rgb_pin_pol; struct vop_reg hdmi_dclk_out_en;
struct vop_reg rgb_dclk_pol; struct vop_reg rgb_en;
struct vop_reg dp_en; struct vop_reg lvds_en;
struct vop_reg edp_en; struct vop_reg edp_en;
struct vop_reg hdmi_en; struct vop_reg hdmi_en;
struct vop_reg mipi_en; struct vop_reg mipi_en;
struct vop_reg data01_swap;
struct vop_reg mipi_dual_channel_en; struct vop_reg mipi_dual_channel_en;
struct vop_reg rgb_en; struct vop_reg dp_en;
}; struct vop_reg dclk_pol;
struct vop_reg pin_pol;
struct vop_common { struct vop_reg rgb_dclk_pol;
struct vop_reg cfg_done; struct vop_reg rgb_pin_pol;
struct vop_reg dsp_blank; struct vop_reg lvds_dclk_pol;
struct vop_reg data_blank; struct vop_reg lvds_pin_pol;
struct vop_reg pre_dither_down; struct vop_reg hdmi_dclk_pol;
struct vop_reg hdmi_pin_pol;
struct vop_reg edp_dclk_pol;
struct vop_reg edp_pin_pol;
struct vop_reg mipi_dclk_pol;
struct vop_reg mipi_pin_pol;
struct vop_reg dp_dclk_pol;
struct vop_reg dp_pin_pol;
struct vop_reg dither_down_sel; struct vop_reg dither_down_sel;
struct vop_reg dither_down_mode; struct vop_reg dither_down_mode;
struct vop_reg dither_down_en; struct vop_reg dither_down_en;
struct vop_reg dither_up; struct vop_reg pre_dither_down_en;
struct vop_reg dsp_lut_en; struct vop_reg dither_up_en;
struct vop_reg gate_en;
struct vop_reg mmu_en;
struct vop_reg out_mode;
struct vop_reg standby;
};
struct vop_misc { struct vop_reg sw_dac_sel;
struct vop_reg global_regdone_en; struct vop_reg tve_sw_mode;
struct vop_reg tve_dclk_pol;
struct vop_reg tve_dclk_en;
struct vop_reg sw_genlock;
struct vop_reg sw_uv_offset_en;
struct vop_reg dsp_out_yuv;
struct vop_reg dsp_data_swap;
struct vop_reg yuv_clip;
struct vop_reg dsp_ccir656_avg;
struct vop_reg dsp_black;
struct vop_reg dsp_blank;
struct vop_reg dsp_outzero;
struct vop_reg update_gamma_lut;
struct vop_reg lut_buffer_index;
struct vop_reg dsp_lut_en;
struct vop_reg out_mode;
struct vop_reg xmirror;
struct vop_reg ymirror;
struct vop_reg dsp_background;
/* AFBDC */
struct vop_reg afbdc_en;
struct vop_reg afbdc_sel;
struct vop_reg afbdc_format;
struct vop_reg afbdc_hreg_block_split;
struct vop_reg afbdc_pic_size;
struct vop_reg afbdc_hdr_ptr;
struct vop_reg afbdc_rstn;
struct vop_reg afbdc_pic_vir_width;
struct vop_reg afbdc_pic_offset;
struct vop_reg afbdc_axi_ctrl;
/* BCSH */
struct vop_reg bcsh_brightness;
struct vop_reg bcsh_contrast;
struct vop_reg bcsh_sat_con;
struct vop_reg bcsh_sin_hue;
struct vop_reg bcsh_cos_hue;
struct vop_reg bcsh_r2y_csc_mode;
struct vop_reg bcsh_r2y_en;
struct vop_reg bcsh_y2r_csc_mode;
struct vop_reg bcsh_y2r_en;
struct vop_reg bcsh_color_bar;
struct vop_reg bcsh_out_mode;
struct vop_reg bcsh_en;
/* HDR */
struct vop_reg level2_overlay_en;
struct vop_reg alpha_hard_calc;
struct vop_reg hdr2sdr_en;
struct vop_reg hdr2sdr_en_win0_csc;
struct vop_reg hdr2sdr_src_min;
struct vop_reg hdr2sdr_src_max;
struct vop_reg hdr2sdr_normfaceetf;
struct vop_reg hdr2sdr_dst_min;
struct vop_reg hdr2sdr_dst_max;
struct vop_reg hdr2sdr_normfacgamma;
struct vop_reg bt1886eotf_pre_conv_en;
struct vop_reg rgb2rgb_pre_conv_en;
struct vop_reg rgb2rgb_pre_conv_mode;
struct vop_reg st2084oetf_pre_conv_en;
struct vop_reg bt1886eotf_post_conv_en;
struct vop_reg rgb2rgb_post_conv_en;
struct vop_reg rgb2rgb_post_conv_mode;
struct vop_reg st2084oetf_post_conv_en;
struct vop_reg win_csc_mode_sel;
/* MCU OUTPUT */
struct vop_reg mcu_pix_total;
struct vop_reg mcu_cs_pst;
struct vop_reg mcu_cs_pend;
struct vop_reg mcu_rw_pst;
struct vop_reg mcu_rw_pend;
struct vop_reg mcu_clk_sel;
struct vop_reg mcu_hold_mode;
struct vop_reg mcu_frame_st;
struct vop_reg mcu_rs;
struct vop_reg mcu_bypass;
struct vop_reg mcu_type;
struct vop_reg mcu_rw_bypass_port;
/* bt1120 */
struct vop_reg bt1120_yc_swap;
struct vop_reg bt1120_en;
struct vop_reg reg_done_frm;
struct vop_reg cfg_done;
}; };
struct vop_intr { struct vop_intr {
const int *intrs; const int *intrs;
uint32_t nintrs; uint32_t nintrs;
struct vop_reg line_flag_num[2]; struct vop_reg line_flag_num[2];
struct vop_reg enable; struct vop_reg enable;
struct vop_reg clear; struct vop_reg clear;
@@ -269,19 +325,129 @@ struct vop_scl_regs {
struct vop_reg scale_cbcr_y; struct vop_reg scale_cbcr_y;
}; };
struct vop_yuv2yuv_phy { struct vop_afbc {
struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS]; struct vop_reg enable;
struct vop_reg win_sel;
struct vop_reg format;
struct vop_reg rb_swap;
struct vop_reg uv_swap;
struct vop_reg auto_gating_en;
struct vop_reg rotate;
struct vop_reg block_split_en;
struct vop_reg pic_vir_width;
struct vop_reg tile_num;
struct vop_reg pic_offset;
struct vop_reg pic_size;
struct vop_reg dsp_offset;
struct vop_reg transform_offset;
struct vop_reg hdr_ptr;
struct vop_reg half_block_en;
struct vop_reg xmirror;
struct vop_reg ymirror;
struct vop_reg rotate_270;
struct vop_reg rotate_90;
struct vop_reg rstn;
};
struct vop_csc_table {
const uint32_t *y2r_bt601;
const uint32_t *y2r_bt601_12_235;
const uint32_t *y2r_bt601_10bit;
const uint32_t *y2r_bt601_10bit_12_235;
const uint32_t *r2y_bt601;
const uint32_t *r2y_bt601_12_235;
const uint32_t *r2y_bt601_10bit;
const uint32_t *r2y_bt601_10bit_12_235;
const uint32_t *y2r_bt709;
const uint32_t *y2r_bt709_10bit;
const uint32_t *r2y_bt709;
const uint32_t *r2y_bt709_10bit;
const uint32_t *y2r_bt2020;
const uint32_t *r2y_bt2020;
const uint32_t *r2r_bt709_to_bt2020;
const uint32_t *r2r_bt2020_to_bt709;
};
struct vop_hdr_table {
const uint32_t hdr2sdr_eetf_oetf_y0_offset;
const uint32_t hdr2sdr_eetf_oetf_y1_offset;
const uint32_t *hdr2sdr_eetf_yn;
const uint32_t *hdr2sdr_bt1886oetf_yn;
const uint32_t hdr2sdr_sat_y0_offset;
const uint32_t hdr2sdr_sat_y1_offset;
const uint32_t *hdr2sdr_sat_yn;
const uint32_t hdr2sdr_src_range_min;
const uint32_t hdr2sdr_src_range_max;
const uint32_t hdr2sdr_normfaceetf;
const uint32_t hdr2sdr_dst_range_min;
const uint32_t hdr2sdr_dst_range_max;
const uint32_t hdr2sdr_normfacgamma;
const uint32_t sdr2hdr_eotf_oetf_y0_offset;
const uint32_t sdr2hdr_eotf_oetf_y1_offset;
const uint32_t *sdr2hdr_bt1886eotf_yn_for_hlg_hdr;
const uint32_t *sdr2hdr_bt1886eotf_yn_for_bt2020;
const uint32_t *sdr2hdr_bt1886eotf_yn_for_hdr;
const uint32_t *sdr2hdr_st2084oetf_yn_for_hlg_hdr;
const uint32_t *sdr2hdr_st2084oetf_yn_for_bt2020;
const uint32_t *sdr2hdr_st2084oetf_yn_for_hdr;
const uint32_t sdr2hdr_oetf_dx_dxpow1_offset;
const uint32_t *sdr2hdr_st2084oetf_dxn_pow2;
const uint32_t *sdr2hdr_st2084oetf_dxn;
const uint32_t sdr2hdr_oetf_xn1_offset;
const uint32_t *sdr2hdr_st2084oetf_xn;
};
enum {
VOP_CSC_Y2R_BT601,
VOP_CSC_Y2R_BT709,
VOP_CSC_Y2R_BT2020,
VOP_CSC_R2Y_BT601,
VOP_CSC_R2Y_BT709,
VOP_CSC_R2Y_BT2020,
VOP_CSC_R2R_BT2020_TO_BT709,
VOP_CSC_R2R_BT709_TO_2020,
};
enum _vop_overlay_mode {
VOP_RGB_DOMAIN,
VOP_YUV_DOMAIN
};
enum _vop_sdr2hdr_func {
SDR2HDR_FOR_BT2020,
SDR2HDR_FOR_HDR,
SDR2HDR_FOR_HLG_HDR,
};
enum _vop_rgb2rgb_conv_mode {
BT709_TO_BT2020,
BT2020_TO_BT709,
};
enum _MCU_IOCTL {
MCU_WRCMD = 0,
MCU_WRDATA,
MCU_SETBYPASS,
}; };
struct vop_win_phy { struct vop_win_phy {
const struct vop_scl_regs *scl; const struct vop_scl_regs *scl;
const uint32_t *data_formats; const uint32_t *data_formats;
uint32_t nformats; uint32_t nformats;
const uint64_t *format_modifiers;
struct vop_reg enable;
struct vop_reg gate; struct vop_reg gate;
struct vop_reg enable;
struct vop_reg format; struct vop_reg format;
struct vop_reg fmt_10;
struct vop_reg fmt_yuyv;
struct vop_reg csc_mode;
struct vop_reg xmirror;
struct vop_reg ymirror;
struct vop_reg rb_swap; struct vop_reg rb_swap;
struct vop_reg act_info; struct vop_reg act_info;
struct vop_reg dsp_info; struct vop_reg dsp_info;
@@ -290,50 +456,25 @@ struct vop_win_phy {
struct vop_reg uv_mst; struct vop_reg uv_mst;
struct vop_reg yrgb_vir; struct vop_reg yrgb_vir;
struct vop_reg uv_vir; struct vop_reg uv_vir;
struct vop_reg y_mir_en;
struct vop_reg x_mir_en;
struct vop_reg channel;
struct vop_reg dst_alpha_ctl; struct vop_reg dst_alpha_ctl;
struct vop_reg src_alpha_ctl; struct vop_reg src_alpha_ctl;
struct vop_reg alpha_pre_mul;
struct vop_reg alpha_mode; struct vop_reg alpha_mode;
struct vop_reg alpha_en; struct vop_reg alpha_en;
struct vop_reg channel; struct vop_reg alpha_pre_mul;
}; struct vop_reg global_alpha_val;
struct vop_reg key_color;
struct vop_win_yuv2yuv_data { struct vop_reg key_en;
uint32_t base;
const struct vop_yuv2yuv_phy *phy;
struct vop_reg y2r_en;
}; };
struct vop_win_data { struct vop_win_data {
uint32_t base; uint32_t base;
const struct vop_win_phy *phy;
enum drm_plane_type type; enum drm_plane_type type;
}; const struct vop_win_phy *phy;
const struct vop_win_phy **area;
struct vop_grf_ctrl { const struct vop_csc *csc;
struct vop_reg grf_dclk_inv; unsigned int area_size;
struct vop_reg grf_bt1120_clk_inv;
struct vop_reg grf_bt656_clk_inv;
};
struct vop_data {
uint32_t version;
const struct vop_intr *intr;
const struct vop_common *common;
const struct vop_misc *misc;
const struct vop_modeset *modeset;
const struct vop_output *output;
const struct vop_afbc *afbc;
const struct vop_win_yuv2yuv_data *win_yuv2yuv;
const struct vop_win_data *win;
unsigned int win_size;
unsigned int lut_size;
#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
#define VOP_FEATURE_INTERNAL_RGB BIT(1)
u64 feature; u64 feature;
}; };
@@ -466,6 +607,7 @@ struct vop2_video_port_regs {
struct vop_reg hdr_dst_color_ctrl; struct vop_reg hdr_dst_color_ctrl;
struct vop_reg hdr_src_alpha_ctrl; struct vop_reg hdr_src_alpha_ctrl;
struct vop_reg hdr_dst_alpha_ctrl; struct vop_reg hdr_dst_alpha_ctrl;
struct vop_reg bg_mix_ctrl;
/* BCSH */ /* BCSH */
struct vop_reg bcsh_brightness; struct vop_reg bcsh_brightness;
@@ -581,7 +723,7 @@ struct vop2_layer_regs {
* *
* The pipeline in vop2: * The pipeline in vop2:
* *
* win-->layer-->mixer-->vp-->connector(RGB/LVDS/HDMI/MIPI) * win-->layer-->mixer-->vp--->connector(RGB/LVDS/HDMI/MIPI)
* *
*/ */
struct vop2_layer_data { struct vop2_layer_data {
@@ -589,6 +731,28 @@ struct vop2_layer_data {
const struct vop2_layer_regs *regs; const struct vop2_layer_regs *regs;
}; };
struct vop_grf_ctrl {
struct vop_reg grf_dclk_inv;
struct vop_reg grf_bt1120_clk_inv;
struct vop_reg grf_bt656_clk_inv;
};
struct vop_data {
const struct vop_reg_data *init_table;
unsigned int table_size;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
const struct vop_csc_table *csc_table;
const struct vop_hdr_table *hdr_table;
const struct vop_grf_ctrl *grf_ctrl;
unsigned int win_size;
uint32_t version;
struct vop_rect max_input;
struct vop_rect max_output;
u64 feature;
};
struct vop2_ctrl { struct vop2_ctrl {
struct vop_reg cfg_done_en; struct vop_reg cfg_done_en;
struct vop_reg wb_cfg_done; struct vop_reg wb_cfg_done;
@@ -699,11 +863,13 @@ struct vop2_data {
unsigned int win_size; unsigned int win_size;
}; };
#define CVBS_PAL_VDISPLAY 288
/* interrupt define */ /* interrupt define */
#define DSP_HOLD_VALID_INTR (1 << 0) #define DSP_HOLD_VALID_INTR BIT(0)
#define FS_INTR (1 << 1) #define FS_INTR BIT(1)
#define LINE_FLAG_INTR (1 << 2) #define LINE_FLAG_INTR BIT(2)
#define BUS_ERROR_INTR (1 << 3) #define BUS_ERROR_INTR BIT(3)
#define FS_NEW_INTR BIT(4) #define FS_NEW_INTR BIT(4)
#define ADDR_SAME_INTR BIT(5) #define ADDR_SAME_INTR BIT(5)
#define LINE_FLAG1_INTR BIT(6) #define LINE_FLAG1_INTR BIT(6)
@@ -730,7 +896,6 @@ struct vop2_data {
POST_BUF_EMPTY_INTR | \ POST_BUF_EMPTY_INTR | \
DMA_FINISH_INTR | FS_FIELD_INTR | \ DMA_FINISH_INTR | FS_FIELD_INTR | \
FE_INTR) FE_INTR)
#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4) #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
#define FS_INTR_EN(x) ((x) << 5) #define FS_INTR_EN(x) ((x) << 5)
#define LINE_FLAG_INTR_EN(x) ((x) << 6) #define LINE_FLAG_INTR_EN(x) ((x) << 6)
@@ -764,10 +929,10 @@ struct vop2_data {
/* /*
* display output interface supported by rockchip lcdc * display output interface supported by rockchip lcdc
*/ */
#define ROCKCHIP_OUT_MODE_P888 0 #define ROCKCHIP_OUT_MODE_P888 0
#define ROCKCHIP_OUT_MODE_BT1120 0 #define ROCKCHIP_OUT_MODE_BT1120 0
#define ROCKCHIP_OUT_MODE_P666 1 #define ROCKCHIP_OUT_MODE_P666 1
#define ROCKCHIP_OUT_MODE_P565 2 #define ROCKCHIP_OUT_MODE_P565 2
#define ROCKCHIP_OUT_MODE_BT656 5 #define ROCKCHIP_OUT_MODE_BT656 5
#define ROCKCHIP_OUT_MODE_S888 8 #define ROCKCHIP_OUT_MODE_S888 8
#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12
@@ -775,13 +940,8 @@ struct vop2_data {
/* for use special outface */ /* for use special outface */
#define ROCKCHIP_OUT_MODE_AAAA 15 #define ROCKCHIP_OUT_MODE_AAAA 15
#define ROCKCHIP_OUT_MODE_TYPE(x) ((x) >> 16)
/* output flags */ #define ROCKCHIP_OUT_MODE(x) ((x) & 0xffff)
#define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0)
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
enum alpha_mode { enum alpha_mode {
ALPHA_STRAIGHT, ALPHA_STRAIGHT,
@@ -810,6 +970,7 @@ enum factor_mode {
ALPHA_SRC, ALPHA_SRC,
ALPHA_SRC_INVERSE, ALPHA_SRC_INVERSE,
ALPHA_SRC_GLOBAL, ALPHA_SRC_GLOBAL,
ALPHA_DST_GLOBAL,
}; };
enum src_factor_mode { enum src_factor_mode {
@@ -880,7 +1041,8 @@ enum dither_down_mode_sel {
enum vop_pol { enum vop_pol {
HSYNC_POSITIVE = 0, HSYNC_POSITIVE = 0,
VSYNC_POSITIVE = 1, VSYNC_POSITIVE = 1,
DEN_NEGATIVE = 2 DEN_NEGATIVE = 2,
DCLK_INVERT = 3
}; };
@@ -908,7 +1070,7 @@ static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
{ {
int act_height; int act_height;
act_height = DIV_ROUND_UP(src_h, vskiplines); act_height = (src_h + vskiplines - 1) / vskiplines;
if (act_height == dst_h) if (act_height == dst_h)
return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines; return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;

2199
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

File diff suppressed because it is too large Load Diff

226
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -113,6 +113,11 @@
#define RK3288_DSP_VACT_ST_END 0x0194 #define RK3288_DSP_VACT_ST_END 0x0194
#define RK3288_DSP_VS_ST_END_F1 0x0198 #define RK3288_DSP_VS_ST_END_F1 0x0198
#define RK3288_DSP_VACT_ST_END_F1 0x019c #define RK3288_DSP_VACT_ST_END_F1 0x019c
#define RK3288_BCSH_COLOR_BAR 0x01b0
#define RK3288_BCSH_BCS 0x01b4
#define RK3288_BCSH_H 0x01b8
#define RK3288_GRF_SOC_CON15 0x03a4
/* register definition end */ /* register definition end */
/* rk3368 register definition */ /* rk3368 register definition */
@@ -300,6 +305,7 @@
#define RK3368_CABC_GAMMA_LUT_ADDR 0x1800 #define RK3368_CABC_GAMMA_LUT_ADDR 0x1800
#define RK3368_MCU_BYPASS_WPORT 0x2200 #define RK3368_MCU_BYPASS_WPORT 0x2200
#define RK3368_MCU_BYPASS_RPORT 0x2300 #define RK3368_MCU_BYPASS_RPORT 0x2300
#define RK3368_GRF_SOC_CON6 0x0418
/* rk3368 register definition end */ /* rk3368 register definition end */
#define RK3366_REG_CFG_DONE 0x0000 #define RK3366_REG_CFG_DONE 0x0000
@@ -628,6 +634,7 @@
#define RK3399_YUV2YUV_WIN 0x02c0 #define RK3399_YUV2YUV_WIN 0x02c0
#define RK3399_YUV2YUV_POST 0x02c4 #define RK3399_YUV2YUV_POST 0x02c4
#define RK3399_AUTO_GATING_EN 0x02cc #define RK3399_AUTO_GATING_EN 0x02cc
#define RK3399_DBG_POST_REG1 0x036c
#define RK3399_WIN0_CSC_COE 0x03a0 #define RK3399_WIN0_CSC_COE 0x03a0
#define RK3399_WIN1_CSC_COE 0x03c0 #define RK3399_WIN1_CSC_COE 0x03c0
#define RK3399_WIN2_CSC_COE 0x03e0 #define RK3399_WIN2_CSC_COE 0x03e0
@@ -798,6 +805,21 @@
#define RK3328_DBG_POST_RESERVED 0x000006ec #define RK3328_DBG_POST_RESERVED 0x000006ec
#define RK3328_DBG_DATAO 0x000006f0 #define RK3328_DBG_DATAO 0x000006f0
#define RK3328_DBG_DATAO_2 0x000006f4 #define RK3328_DBG_DATAO_2 0x000006f4
#define RK3328_SDR2HDR_CTRL 0x00000700
#define RK3328_SDR2HDR_EOTF_OETF_Y0 0x00000704
#define RK3328_SDR2HDR_EOTF_OETF_Y1 0x00000710
#define RK3328_SDR2HDR_OETF_DX_DXPOW1 0x00000810
#define RK3328_SDR2HDR_OETF_XN1 0x00000910
#define RK3328_HDR2DR_CTRL 0x00000a10
#define RK3328_HDR2DR_SRC_RANGE 0x00000a14
#define RK3328_HDR2DR_NORMFACEETF 0x00000a18
#define RK3328_HDR2DR_DST_RANGE 0x00000a20
#define RK3328_HDR2DR_NORMFACGAMMA 0x00000a24
#define RK3328_HDR2SDR_EETF_OETF_Y0 0x00000a28
#define RK3328_HDR2DR_SAT_Y0 0x00000a2C
#define RK3328_HDR2SDR_EETF_OETF_Y1 0x00000a30
#define RK3328_HDR2DR_SAT_Y1 0x00000ab0
/* sdr to hdr */ /* sdr to hdr */
#define RK3328_SDR2HDR_CTRL 0x00000700 #define RK3328_SDR2HDR_CTRL 0x00000700
@@ -830,6 +852,7 @@
#define RK3036_SYS_CTRL 0x00 #define RK3036_SYS_CTRL 0x00
#define RK3036_DSP_CTRL0 0x04 #define RK3036_DSP_CTRL0 0x04
#define RK3036_DSP_CTRL1 0x08 #define RK3036_DSP_CTRL1 0x08
#define RK3036_INT_SCALER 0x0c
#define RK3036_INT_STATUS 0x10 #define RK3036_INT_STATUS 0x10
#define RK3036_ALPHA_CTRL 0x14 #define RK3036_ALPHA_CTRL 0x14
#define RK3036_WIN0_COLOR_KEY 0x18 #define RK3036_WIN0_COLOR_KEY 0x18
@@ -870,112 +893,6 @@
#define RK3036_HWC_LUT_ADDR 0x800 #define RK3036_HWC_LUT_ADDR 0x800
/* rk3036 register definition end */ /* rk3036 register definition end */
/* rk3126 register definition */
#define RK3126_WIN1_MST 0x4c
#define RK3126_WIN1_DSP_INFO 0x50
#define RK3126_WIN1_DSP_ST 0x54
/* rk3126 register definition end */
/* px30 register definition */
#define PX30_REG_CFG_DONE 0x00000
#define PX30_VERSION 0x00004
#define PX30_DSP_BG 0x00008
#define PX30_MCU_CTRL 0x0000c
#define PX30_SYS_CTRL0 0x00010
#define PX30_SYS_CTRL1 0x00014
#define PX30_SYS_CTRL2 0x00018
#define PX30_DSP_CTRL0 0x00020
#define PX30_DSP_CTRL2 0x00028
#define PX30_VOP_STATUS 0x0002c
#define PX30_LINE_FLAG 0x00030
#define PX30_INTR_EN 0x00034
#define PX30_INTR_CLEAR 0x00038
#define PX30_INTR_STATUS 0x0003c
#define PX30_WIN0_CTRL0 0x00050
#define PX30_WIN0_CTRL1 0x00054
#define PX30_WIN0_COLOR_KEY 0x00058
#define PX30_WIN0_VIR 0x0005c
#define PX30_WIN0_YRGB_MST0 0x00060
#define PX30_WIN0_CBR_MST0 0x00064
#define PX30_WIN0_ACT_INFO 0x00068
#define PX30_WIN0_DSP_INFO 0x0006c
#define PX30_WIN0_DSP_ST 0x00070
#define PX30_WIN0_SCL_FACTOR_YRGB 0x00074
#define PX30_WIN0_SCL_FACTOR_CBR 0x00078
#define PX30_WIN0_SCL_OFFSET 0x0007c
#define PX30_WIN0_ALPHA_CTRL 0x00080
#define PX30_WIN1_CTRL0 0x00090
#define PX30_WIN1_CTRL1 0x00094
#define PX30_WIN1_VIR 0x00098
#define PX30_WIN1_MST 0x000a0
#define PX30_WIN1_DSP_INFO 0x000a4
#define PX30_WIN1_DSP_ST 0x000a8
#define PX30_WIN1_COLOR_KEY 0x000ac
#define PX30_WIN1_ALPHA_CTRL 0x000bc
#define PX30_HWC_CTRL0 0x000e0
#define PX30_HWC_CTRL1 0x000e4
#define PX30_HWC_MST 0x000e8
#define PX30_HWC_DSP_ST 0x000ec
#define PX30_HWC_ALPHA_CTRL 0x000f0
#define PX30_DSP_HTOTAL_HS_END 0x00100
#define PX30_DSP_HACT_ST_END 0x00104
#define PX30_DSP_VTOTAL_VS_END 0x00108
#define PX30_DSP_VACT_ST_END 0x0010c
#define PX30_DSP_VS_ST_END_F1 0x00110
#define PX30_DSP_VACT_ST_END_F1 0x00114
#define PX30_BCSH_CTRL 0x00160
#define PX30_BCSH_COL_BAR 0x00164
#define PX30_BCSH_BCS 0x00168
#define PX30_BCSH_H 0x0016c
#define PX30_FRC_LOWER01_0 0x00170
#define PX30_FRC_LOWER01_1 0x00174
#define PX30_FRC_LOWER10_0 0x00178
#define PX30_FRC_LOWER10_1 0x0017c
#define PX30_FRC_LOWER11_0 0x00180
#define PX30_FRC_LOWER11_1 0x00184
#define PX30_MCU_RW_BYPASS_PORT 0x0018c
#define PX30_WIN2_CTRL0 0x00190
#define PX30_WIN2_CTRL1 0x00194
#define PX30_WIN2_VIR0_1 0x00198
#define PX30_WIN2_VIR2_3 0x0019c
#define PX30_WIN2_MST0 0x001a0
#define PX30_WIN2_DSP_INFO0 0x001a4
#define PX30_WIN2_DSP_ST0 0x001a8
#define PX30_WIN2_COLOR_KEY 0x001ac
#define PX30_WIN2_ALPHA_CTRL 0x001bc
#define PX30_BLANKING_VALUE 0x001f4
#define PX30_FLAG_REG_FRM_VALID 0x001f8
#define PX30_FLAG_REG 0x001fc
#define PX30_HWC_LUT_ADDR 0x00600
#define PX30_GAMMA_LUT_ADDR 0x00a00
/* px30 register definition end */
/* rk3188 register definition */
#define RK3188_SYS_CTRL 0x00
#define RK3188_DSP_CTRL0 0x04
#define RK3188_DSP_CTRL1 0x08
#define RK3188_INT_STATUS 0x10
#define RK3188_WIN0_YRGB_MST0 0x20
#define RK3188_WIN0_CBR_MST0 0x24
#define RK3188_WIN0_YRGB_MST1 0x28
#define RK3188_WIN0_CBR_MST1 0x2c
#define RK3188_WIN_VIR 0x30
#define RK3188_WIN0_ACT_INFO 0x34
#define RK3188_WIN0_DSP_INFO 0x38
#define RK3188_WIN0_DSP_ST 0x3c
#define RK3188_WIN0_SCL_FACTOR_YRGB 0x40
#define RK3188_WIN0_SCL_FACTOR_CBR 0x44
#define RK3188_WIN1_MST 0x4c
#define RK3188_WIN1_DSP_INFO 0x50
#define RK3188_WIN1_DSP_ST 0x54
#define RK3188_DSP_HTOTAL_HS_END 0x6c
#define RK3188_DSP_HACT_ST_END 0x70
#define RK3188_DSP_VTOTAL_VS_END 0x74
#define RK3188_DSP_VACT_ST_END 0x78
#define RK3188_REG_CFG_DONE 0x90
/* rk3188 register definition end */
/* rk3066 register definition */
#define RK3066_SYS_CTRL0 0x00 #define RK3066_SYS_CTRL0 0x00
#define RK3066_SYS_CTRL1 0x04 #define RK3066_SYS_CTRL1 0x04
#define RK3066_DSP_CTRL0 0x08 #define RK3066_DSP_CTRL0 0x08
@@ -1026,7 +943,101 @@
#define RK3066_MCU_BYPASS_RPORT 0x200 #define RK3066_MCU_BYPASS_RPORT 0x200
#define RK3066_WIN2_LUT_ADDR 0x400 #define RK3066_WIN2_LUT_ADDR 0x400
#define RK3066_DSP_LUT_ADDR 0x800 #define RK3066_DSP_LUT_ADDR 0x800
/* rk3066 register definition end */
/* rk3366 register definition */
#define RK3366_LIT_REG_CFG_DONE 0x00000
#define RK3366_LIT_VERSION 0x00004
#define RK3366_LIT_DSP_BG 0x00008
#define RK3366_LIT_MCU_CTRL 0x0000c
#define RK3366_LIT_SYS_CTRL0 0x00010
#define RK3366_LIT_SYS_CTRL1 0x00014
#define RK3366_LIT_SYS_CTRL2 0x00018
#define RK3366_LIT_DSP_CTRL0 0x00020
#define RK3366_LIT_DSP_CTRL2 0x00028
#define RK3366_LIT_VOP_STATUS 0x0002c
#define RK3366_LIT_LINE_FLAG 0x00030
#define RK3366_LIT_INTR_EN 0x00034
#define RK3366_LIT_INTR_CLEAR 0x00038
#define RK3366_LIT_INTR_STATUS 0x0003c
#define RK3366_LIT_WIN0_CTRL0 0x00050
#define RK3366_LIT_WIN0_CTRL1 0x00054
#define RK3366_LIT_WIN0_COLOR_KEY 0x00058
#define RK3366_LIT_WIN0_VIR 0x0005c
#define RK3366_LIT_WIN0_YRGB_MST0 0x00060
#define RK3366_LIT_WIN0_CBR_MST0 0x00064
#define RK3366_LIT_WIN0_ACT_INFO 0x00068
#define RK3366_LIT_WIN0_DSP_INFO 0x0006c
#define RK3366_LIT_WIN0_DSP_ST 0x00070
#define RK3366_LIT_WIN0_SCL_FACTOR_YRGB 0x00074
#define RK3366_LIT_WIN0_SCL_FACTOR_CBR 0x00078
#define RK3366_LIT_WIN0_SCL_OFFSET 0x0007c
#define RK3366_LIT_WIN0_ALPHA_CTRL 0x00080
#define RK3366_LIT_WIN1_CTRL0 0x00090
#define RK3366_LIT_WIN1_CTRL1 0x00094
#define RK3366_LIT_WIN1_VIR 0x00098
#define RK3366_LIT_WIN1_MST 0x000a0
#define RK3366_LIT_WIN1_DSP_INFO 0x000a4
#define RK3366_LIT_WIN1_DSP_ST 0x000a8
#define RK3366_LIT_WIN1_COLOR_KEY 0x000ac
#define RK3366_LIT_WIN1_ALPHA_CTRL 0x000bc
#define RK3366_LIT_HWC_CTRL0 0x000e0
#define RK3366_LIT_HWC_CTRL1 0x000e4
#define RK3366_LIT_HWC_MST 0x000e8
#define RK3366_LIT_HWC_DSP_ST 0x000ec
#define RK3366_LIT_HWC_ALPHA_CTRL 0x000f0
#define RK3366_LIT_DSP_HTOTAL_HS_END 0x00100
#define RK3366_LIT_DSP_HACT_ST_END 0x00104
#define RK3366_LIT_DSP_VTOTAL_VS_END 0x00108
#define RK3366_LIT_DSP_VACT_ST_END 0x0010c
#define RK3366_LIT_DSP_VS_ST_END_F1 0x00110
#define RK3366_LIT_DSP_VACT_ST_END_F1 0x00114
#define RK3366_LIT_BCSH_CTRL 0x00160
#define RK3366_LIT_BCSH_COL_BAR 0x00164
#define RK3366_LIT_BCSH_BCS 0x00168
#define RK3366_LIT_BCSH_H 0x0016c
#define RK3366_LIT_FRC_LOWER01_0 0x00170
#define RK3366_LIT_FRC_LOWER01_1 0x00174
#define RK3366_LIT_FRC_LOWER10_0 0x00178
#define RK3366_LIT_FRC_LOWER10_1 0x0017c
#define RK3366_LIT_FRC_LOWER11_0 0x00180
#define RK3366_LIT_FRC_LOWER11_1 0x00184
#define RK3366_LIT_MCU_RW_BYPASS_PORT 0x0018c
#define RK3366_LIT_DBG_REG_000 0x00190
#define RK3366_LIT_BLANKING_VALUE 0x001f4
#define RK3366_LIT_FLAG_REG_FRM_VALID 0x001f8
#define RK3366_LIT_FLAG_REG 0x001fc
#define RK3366_LIT_HWC_LUT_ADDR 0x00600
#define RK3366_LIT_GAMMA_LUT_ADDR 0x00a00
/* rk3366 register definition end */
/* rk3126 register definition */
#define RK3126_WIN1_MST 0x0004c
#define RK3126_WIN1_DSP_INFO 0x00050
#define RK3126_WIN1_DSP_ST 0x00054
/* rk3126 register definition end */
/* px30 register definition */
#define PX30_CABC_CTRL0 0x00200
#define PX30_CABC_CTRL1 0x00204
#define PX30_CABC_CTRL2 0x00208
#define PX30_CABC_CTRL3 0x0020c
#define PX30_CABC_GAUSS_LINE0_0 0x00210
#define PX30_CABC_GAUSS_LINE0_1 0x00214
#define PX30_CABC_GAUSS_LINE1_0 0x00218
#define PX30_CABC_GAUSS_LINE1_1 0x0021c
#define PX30_CABC_GAUSS_LINE2_0 0x00220
#define PX30_CABC_GAUSS_LINE2_1 0x00224
#define PX30_AFBCD0_CTRL 0x00240
#define PX30_AFBCD0_HDR_PTR 0x00244
#define PX30_AFBCD0_PIC_SIZE 0x00248
#define PX30_AFBCD0_PIC_OFFSET 0x0024c
#define PX30_AFBCD0_AXI_CTRL 0x00250
#define PX30_GRF_PD_VO_CON1 0x00438
/* px30 register definition end */
#define RV1126_GRF_IOFUNC_CON3 0x1026c
/* rk3568 vop registers definition */
#define RK3568_GRF_VO_CON1 0x0364 #define RK3568_GRF_VO_CON1 0x0364
/* System registers definition */ /* System registers definition */
@@ -1443,5 +1454,4 @@
#define RK3568_HDR_EOTF_OETF_Y0 0x20F0 #define RK3568_HDR_EOTF_OETF_Y0 0x20F0
#define RK3568_HDR_OETF_DX_POW1 0x2200 #define RK3568_HDR_OETF_DX_POW1 0x2200
#define RK3568_HDR_OETF_XN1 0x2300 #define RK3568_HDR_OETF_XN1 0x2300
#endif /* _ROCKCHIP_VOP_REG_H */ #endif /* _ROCKCHIP_VOP_REG_H */