From fa7692e1ca7d883d0a949901f7abe515c509e653 Mon Sep 17 00:00:00 2001 From: Meng Dongyang Date: Mon, 11 Sep 2017 18:29:19 +0800 Subject: [PATCH] usb: dwc2: increase delay time after reset for rk312x According DWC-OTG databook, after the CSftRst bit is cleared, the application must wait at least 3 PHY clocks before doing any access to the PHY domain. And longer delay is required for some rockchip soc based platforms. But current delay time is not long enough for rk312x and it will result in repeately trigger of ID change interrupt of dwc2 controller. This patch increase delay time from 50 millisecond to 80 millisecond to make sure that dwc2 controller and PHY is synchronized. Change-Id: I4aa5cc3a4ceb8f3e3907c0563ed56ec4a3853a2d Signed-off-by: Meng Dongyang --- drivers/usb/dwc2/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c index 4135a5ff67ca..e9851f2d4219 100644 --- a/drivers/usb/dwc2/core.c +++ b/drivers/usb/dwc2/core.c @@ -385,7 +385,7 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) * NOTE: This is required for some rockchip soc based * platforms. */ - msleep(50); + msleep(80); } /*