From fb7d7606a1069afb75653f73412fead2a4e2aaf2 Mon Sep 17 00:00:00 2001
From: Tao Huang <huangtao@rock-chips.com>
Date: Thu, 11 Nov 2021 17:18:31 +0800
Subject: [PATCH] clk: rockchip: Temporarily fix for rk3588 pll

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I15819f3611556e140ec80126b990408edf260c18
---
 drivers/clk/rockchip/clk-pll.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 3bd161d066ec..34056e83480e 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1268,6 +1268,9 @@ static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)
 	u32 pllcon;
 	int ret;
 
+	for (ret = 0; ret < 1000; ret++)
+		asm("nop");
+	return 0;
 	/*
 	 * Lock time typical 250, max 500 input clock cycles @24MHz
 	 * So define a very safe maximum of 1000us, meaning 24000 cycles.