From fbb6fa05c76c8ef91a47f15bfcc964cf717fb79e Mon Sep 17 00:00:00 2001
From: Frank Wang <frank.wang@rock-chips.com>
Date: Tue, 1 Mar 2022 09:34:42 +0800
Subject: [PATCH] ARM: dts: rockchip: rv1106: add mailbox nodes

This adds mailbox and pmu_mailbox nodes for RV1106 SoCs.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I2c1f6c9f64f0ec04d981c1491495611bc2cff09a
---
 arch/arm/boot/dts/rv1106.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi
index 8eebc42488d8..d1942f9a09bb 100644
--- a/arch/arm/boot/dts/rv1106.dtsi
+++ b/arch/arm/boot/dts/rv1106.dtsi
@@ -190,6 +190,17 @@
 		status = "disabled";
 	};
 
+	pmu_mailbox: mailbox@ff378000 {
+		compatible = "rockchip,rv1106-mailbox",
+			     "rockchip,rk3368-mailbox";
+		reg = <0xff378000 0x200>;
+		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_PMU_MAILBOX>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
 	pmuioc: syscon@ff388000 {
 		compatible = "rockchip,rv1106-pmuioc", "syscon";
 		reg = <0xff388000 0x1000>;
@@ -494,6 +505,17 @@
 		status = "disabled";
 	};
 
+	mailbox: mailbox@ff5c0000 {
+		compatible = "rockchip,rv1106-mailbox",
+			     "rockchip,rk3368-mailbox";
+		reg = <0xff5c0000 0x200>;
+		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_MAILBOX>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
 	rga2: rga@ff980000 {
 		compatible = "rockchip,rga2_core0";
 		reg = <0xff980000 0x1000>;