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fixed: pm-rk3288.c

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xxx
2014-03-18 19:56:56 +08:00
parent c0a65262f7
commit fbf2018630
5 changed files with 1087 additions and 4 deletions
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19
arch/arm/boot/dts/rk3288.dtsi
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@@ -785,6 +785,21 @@
compatible = "iommu,vopl_mmu";
reg = <0xffa40000 0x10000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
};
interrupt-names = "vopl_mmu";};
rockchip_suspend {
rockchip,ctrbits = <
(0
// RKPM_CTR_PWR_DMNS
//|RKPM_CTR_GTCLKS
//|RKPM_CTR_PLLS
//|RKPM_CTR_SYSCLK_DIV
|RKPM_CTR_NORIDLE_MD
)
>;
rockchip,pmic-gpios=<
RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
>;
};
};

1020
arch/arm/mach-rockchip/pm-rk3288.c Executable file
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File diff suppressed because it is too large Load Diff

15
arch/arm/mach-rockchip/rk3288.c Executable file → Normal file
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@@ -73,6 +73,9 @@ static struct map_desc rk3288_io_desc[] __initdata = {
RK_DEVICE(RK_GPIO_VIRT(7), RK3288_GPIO7_PHYS, RK3288_GPIO_SIZE),
RK_DEVICE(RK_GPIO_VIRT(8), RK3288_GPIO8_PHYS, RK3288_GPIO_SIZE),
RK_DEVICE(RK_DEBUG_UART_VIRT, RK3288_UART_DBG_PHYS, RK3288_UART_SIZE),
RK_DEVICE(RK_GIC_VIRT, RK3288_GIC_DIST_PHYS, RK3288_GIC_DIST_SIZE),
RK_DEVICE(RK_GIC_VIRT+RK3288_GIC_DIST_SIZE, RK3288_GIC_DIST_PHYS+RK3288_GIC_DIST_SIZE, RK3288_GIC_CPU_SIZE),
};
static void __init rk3288_boot_mode_init(void)
@@ -339,6 +342,7 @@ static void rk3288_restart(char mode, const char *cmd)
writel_relaxed(0xeca8, RK_CRU_VIRT + RK3288_CRU_GLB_SRST_SND_VALUE);
dsb();
}
static void __init rk3288_init_suspend(void);
DT_MACHINE_START(RK3288_DT, "RK30board")
.smp = smp_ops(rockchip_smp_ops),
@@ -346,7 +350,7 @@ DT_MACHINE_START(RK3288_DT, "RK30board")
.init_time = rk3288_dt_init_timer,
.dt_compat = rk3288_dt_compat,
#ifdef CONFIG_PM
.init_late = rockchip_suspend_init,
.init_late = rk3288_init_suspend,
#endif
.reserve = rk3288_reserve,
.restart = rk3288_restart,
@@ -381,3 +385,12 @@ static int __init rk3288_pie_init(void)
return 0;
}
arch_initcall(rk3288_pie_init);
#ifdef CONFIG_PM
#include "pm-rk3288.c"
static void __init rk3288_init_suspend(void)
{
rockchip_suspend_init();
rkpm_pie_init();
rk3288_suspend_init();
}
#endif

30
include/linux/rockchip/cru.h Normal file → Executable file
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@@ -5,8 +5,11 @@
/*******************CRU BITS*******************************/
#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
#define CRU_SET_BITS(val, bits_shift, msk) (((val)&(msk)) << (bits_shift))
#define CRU_W_MSK_SETBITS(val, bits_shift,msk) \
(CRU_W_MSK(bits_shift, msk) | CRU_SET_BITS(val, bits_shift, msk))
@@ -39,8 +42,11 @@
#define RK3188_PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
#define RK3188_PLL_MODE_DEEP(id) ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
/******************CRU GATINGS**********************************/
#define RK3188_CRU_GATEID_CONS(ID) (RK3188_CRU_CLKGATE_CON+(ID/16)*4)
/*************************RK3288********************************/
/*******************RK3288********************************/
/*******************CRU OFFSET*********************/
#define RK3288_CRU_MODE_CON 0x50
#define RK3288_CRU_CLKSEL_CON 0x60
@@ -50,6 +56,28 @@
#define RK3288_CRU_CLKSELS_CON(i) (RK3288_CRU_CLKSEL_CON + ((i) * 4))
#define RK3288_CRU_CLKGATES_CON(i) (RK3288_CRU_CLKGATE_CON + ((i) * 4))
/******************PLL MODE BITS*******************/
// apll dpll,cpll,gpll,npll 0~4
#define RK3288_PLLS_MODE_OFFSET(id) ((id)<=3 ? (id*4) : 14)
#define RK3288_PLL_MODE_MSK(id) (0x3 << RK3288_PLLS_MODE_OFFSET(id))
#define RK3288_PLL_MODE_SLOW(id) ((0x0<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
#define RK3288_PLL_MODE_NORM(id) ((0x1<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
#define RK3288_PLL_MODE_DEEP(id) ((0x2<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
/*******************CRU GATING*********************/
#define RK3288_CRU_CLKGATES_CON_CNT (19)
#define RK3288_CRU_CONS_GATEID(i) (16 * (i))
#define RK3288_CRU_GATEID_CONS(ID) (RK3288_CRU_CLKGATE_CON+(ID/16)*4)
enum rk3288_cru_clk_gate {
/* SCU CLK GATE 0 CON */
//gate0
RK3288_CLKGATE_UART0_SRC= (RK3288_CRU_CONS_GATEID(1)+8),
//gate6
RK3288_CLKGATE_PCLK_UART0= (RK3288_CRU_CONS_GATEID(6)+6),
};
#define RK3288_CRU_GLB_SRST_FST_VALUE 0x1b0
#define RK3288_CRU_GLB_SRST_SND_VALUE 0x1b4
#define RK3288_CRU_MISC_CON 0x1e8

7
include/linux/rockchip/iomap.h Normal file → Executable file
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@@ -17,8 +17,10 @@
#define RK_DEBUG_UART_VIRT RK_IO_ADDRESS(0x00060000)
#define RK_CPU_AXI_BUS_VIRT RK_IO_ADDRESS(0x00070000)
#define RK_TIMER_VIRT RK_IO_ADDRESS(0x00080000)
#define RK_GIC_VIRT RK_IO_ADDRESS(0x00090000)
#define RK_DDR_VIRT RK_IO_ADDRESS(0x000d0000)
#define RK3188_CRU_PHYS 0x20000000
#define RK3188_CRU_SIZE SZ_4K
#define RK3188_GRF_PHYS 0x20008000
@@ -103,4 +105,9 @@
#define RK3288_UART_EXP_PHYS 0xFF1C0000
#define RK3288_UART_SIZE SZ_4K
#define RK3288_GIC_DIST_PHYS 0xffc01000
#define RK3288_GIC_DIST_SIZE SZ_4K
#define RK3288_GIC_CPU_PHYS 0xffc02000
#define RK3288_GIC_CPU_SIZE SZ_4K
#endif