From fc3b3a7e3d87fe528bb9cd655e540d4e4a3b45c7 Mon Sep 17 00:00:00 2001 From: Bencheng Jing Date: Wed, 17 Apr 2019 11:26:58 +0800 Subject: [PATCH] amvecm: fix sm1 green screen when play videos [1/1] PD#SWPL-7302 Problem: sm1 green screen when play videos Solution: add chip support Verify: s905D3 Change-Id: I50c0a9f889d72b65157a973bfe1df8dce10db64a Signed-off-by: Bencheng Jing Conflicts: drivers/amlogic/media/enhancement/amvecm/amve.c --- .../amlogic/media/enhancement/amvecm/amve.c | 9 +++ .../amlogic/media/enhancement/amvecm/amve.h | 1 + .../amlogic/media/enhancement/amvecm/amvecm.c | 15 +++-- .../media/enhancement/amvecm/set_hdr2_v0.c | 8 --- .../amlogic/media/enhancement/amvecm/vlock.c | 66 +++++++++++++++---- 5 files changed, 72 insertions(+), 27 deletions(-) diff --git a/drivers/amlogic/media/enhancement/amvecm/amve.c b/drivers/amlogic/media/enhancement/amvecm/amve.c index ec20427479b3..53b6dd9e890e 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amve.c +++ b/drivers/amlogic/media/enhancement/amvecm/amve.c @@ -1324,6 +1324,9 @@ void amvecm_3d_sync_process(void) #define SR_NOSCALE_LEVEL 0x10 static void amve_sr_reg_setting(unsigned int adaptive_level) { + if (is_meson_g12a_cpu() || is_meson_g12b_cpu() || + is_meson_sm1_cpu()) + goto g12_sr_reg_setting; if (adaptive_level & SR_SD_SCALE_LEVEL) am_set_regmap(&sr1reg_sd_scale); else if (adaptive_level & SR_HD_SCALE_LEVEL) @@ -1340,6 +1343,12 @@ static void amve_sr_reg_setting(unsigned int adaptive_level) am_set_regmap(&sr1reg_cvbs); else if (adaptive_level & SR_NOSCALE_LEVEL) am_set_regmap(&sr1reg_hv_noscale); + return; +g12_sr_reg_setting: + /*for g12a and g12b, load sr0 cvbs table when output cvbs mode*/ + if (adaptive_level & SR_CVBS_LEVEL) + am_set_regmap(&sr0reg_cvbs); + return; } void amve_sharpness_adaptive_setting(struct vframe_s *vf, unsigned int sps_h_en, unsigned int sps_v_en) diff --git a/drivers/amlogic/media/enhancement/amvecm/amve.h b/drivers/amlogic/media/enhancement/amvecm/amve.h index 6963dfe5473c..02110178715a 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amve.h +++ b/drivers/amlogic/media/enhancement/amvecm/amve.h @@ -157,6 +157,7 @@ extern void amve_sharpness_adaptive_setting(struct vframe_s *vf, extern void amve_sharpness_init(void); extern struct am_regs_s sr1reg_sd_scale; extern struct am_regs_s sr1reg_hd_scale; +extern struct am_regs_s sr0reg_cvbs; extern struct am_regs_s sr1reg_cvbs; extern struct am_regs_s sr1reg_hv_noscale; extern void amvecm_fresh_overscan(struct vframe_s *vf); diff --git a/drivers/amlogic/media/enhancement/amvecm/amvecm.c b/drivers/amlogic/media/enhancement/amvecm/amvecm.c index e92a2320bfcc..7a0e6d43e252 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amvecm.c +++ b/drivers/amlogic/media/enhancement/amvecm/amvecm.c @@ -131,7 +131,7 @@ unsigned int atv_source_flg; static int vdj_mode_flg; struct am_vdj_mode_s vdj_mode_s; -void __iomem *amvecm_hiu_reg_base;/* = *ioremap(0xc883c000, 0x2000); */ +/*void __iomem *amvecm_hiu_reg_base;*//* = *ioremap(0xc883c000, 0x2000); */ static int debug_amvecm; module_param(debug_amvecm, int, 0664); @@ -724,6 +724,7 @@ static ssize_t amvecm_vlock_store(struct class *cla, sel = VLOCK_SUPPORT; } else if (!strncmp(parm[0], "enable", 6)) { vecm_latch_flag |= FLAG_VLOCK_EN; + vlock_set_en(true); } else if (!strncmp(parm[0], "disable", 7)) { vecm_latch_flag |= FLAG_VLOCK_DIS; } else if (!strncmp(parm[0], "status", 6)) { @@ -1110,7 +1111,8 @@ int amvecm_on_vs( /* add some flag to trigger */ if (vf) { /*gxlx sharpness adaptive setting*/ - if (is_meson_gxlx_cpu()) + if (is_meson_gxlx_cpu() || is_meson_g12a_cpu() + || is_meson_g12b_cpu() || is_meson_sm1_cpu()) amve_sharpness_adaptive_setting(vf, sps_h_en, sps_v_en); amvecm_bricon_process( @@ -6847,16 +6849,19 @@ static struct platform_driver aml_vecm_driver = { static int __init aml_vecm_init(void) { - unsigned int hiu_reg_base; + /*unsigned int hiu_reg_base;*/ pr_info("%s:module init\n", __func__); + #if 0 /* remap the hiu bus */ if (is_meson_txlx_cpu() || is_meson_txhd_cpu() || - is_meson_g12a_cpu() || is_meson_g12b_cpu()) + is_meson_g12a_cpu() || is_meson_g12b_cpu() + || is_meson_tl1_cpu()) hiu_reg_base = 0xff63c000; else hiu_reg_base = 0xc883c000; amvecm_hiu_reg_base = ioremap(hiu_reg_base, 0x2000); + #endif if (platform_driver_register(&aml_vecm_driver)) { pr_err("failed to register bl driver module\n"); return -ENODEV; @@ -6868,7 +6873,7 @@ static int __init aml_vecm_init(void) static void __exit aml_vecm_exit(void) { pr_info("%s:module exit\n", __func__); - iounmap(amvecm_hiu_reg_base); + /*iounmap(amvecm_hiu_reg_base);*/ platform_driver_unregister(&aml_vecm_driver); } diff --git a/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c b/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c index d4ab598a4dc5..f28f66561c79 100644 --- a/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c +++ b/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c @@ -1301,14 +1301,6 @@ void set_hdr_matrix( adpscl_alpha[i] = 10 * in_luma * (1 << adp_scal_shift) / out_luma; - if (hdr_mtx_param->p_sel & HDR_SDR) { - if (i == 0) - adpscl_shift[i] = adp_scal_shift; - else - adpscl_shift[i] = adp_scal_shift - 2; - } else - adpscl_shift[i] = adp_scal_shift; - adpscl_ys_coef[i] = 1 << adp_scal_shift; adpscl_beta_s[i] = 0; diff --git a/drivers/amlogic/media/enhancement/amvecm/vlock.c b/drivers/amlogic/media/enhancement/amvecm/vlock.c index 6fba57dfe9b4..49477b525bef 100644 --- a/drivers/amlogic/media/enhancement/amvecm/vlock.c +++ b/drivers/amlogic/media/enhancement/amvecm/vlock.c @@ -315,10 +315,9 @@ static void vlock_enable(bool enable) { unsigned int tmp_value; - amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL6, &tmp_value); - if (is_meson_gxtvbb_cpu()) { if (vlock_mode & VLOCK_MODE_MANUAL_PLL) { + amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL6, &tmp_value); amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, 0, 20, 1); /*vlsi suggest config:don't enable load signal, *on gxtvbb this load signal will effect SSG, @@ -352,6 +351,9 @@ static void vlock_enable(bool enable) /*WRITE_VPP_REG(VPU_VLOCK_CTRL, 0);*/ } } + + if (vlock_debug & VLOCK_DEBUG_INFO) + pr_info(">>>[%s] (%d)\n", __func__, enable); } static void vlock_hw_reinit(struct vlock_regs_s *vlock_regs, unsigned int len) { @@ -361,6 +363,9 @@ static void vlock_hw_reinit(struct vlock_regs_s *vlock_regs, unsigned int len) return; for (i = 0; i < len; i++) WRITE_VPP_REG(vlock_regs[i].addr, vlock_regs[i].val); + + if (vlock_debug & VLOCK_DEBUG_INFO) + pr_info("[%s]\n", __func__); } static void vlock_setting(struct vframe_s *vf, unsigned int input_hz, unsigned int output_hz) @@ -568,19 +573,18 @@ static void vlock_setting(struct vframe_s *vf, else if (vf->source_type == VFRAME_SOURCE_TYPE_HDMI) /* Input Vsync source select from hdmi-rx */ WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 16, 3); + + /*enable vlock*/ WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 31, 1); } void vlock_vmode_check(void) { const struct vinfo_s *vinfo; - unsigned int t0, t1, hiu_reg_addr; + unsigned int t0, t1; if (vlock_en == 0) return; - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) - hiu_reg_addr = HHI_HDMI_PLL_CNTL1; - else - hiu_reg_addr = HHI_HDMI_PLL_CNTL2; + vinfo = get_current_vinfo(); vlock_vmode_changed = 0; if ((vlock_notify_event == VOUT_EVENT_MODE_CHANGE) || @@ -813,10 +817,13 @@ static void vlock_enable_step1(struct vframe_s *vf, struct vinfo_s *vinfo, vlock_sync_limit_flag = 0; vlock_vmode_changed = 0; vlock_dis_cnt = 0; - vlock_state = VLOCK_STATE_ENABLE_STEP1_DONE; + /*vlock_state = VLOCK_STATE_ENABLE_STEP1_DONE;*/ vlock_pll_stable_cnt = 0; vlock_log_cnt = 0; vlock_enc_stable_flag = 0; + + if (vlock_debug & VLOCK_DEBUG_INFO) + pr_info(">>>[%s]\n", __func__); } void vlock_log_start(void) @@ -944,6 +951,8 @@ static void vlock_enable_step3_enc(void) vlock_reg_get(); vlock_log_cnt++; } + if (vlock_debug & VLOCK_DEBUG_INFO) + pr_info(">>>[%s]\n", __func__); } static void vlock_enable_step3_soft_enc(void) @@ -1052,7 +1061,7 @@ static void vlock_enable_step3_soft_enc(void) WRITE_VPP_REG(ENCL_VIDEO_MAX_LNCNT, pre_enc_max_line + line_adj); if (!(vlock_debug & VLOCK_DEBUG_ENC_PIXEL_ADJ_DIS)) - WRITE_VPP_REG(ENCL_MAX_LINE_SWITCH_POINT, + WRITE_VPP_REG(enc_max_line_switch_addr, pre_enc_max_pixel + pixel_adj); last_i_vsync = READ_VPP_REG(0x3011); @@ -1069,7 +1078,10 @@ static void vlock_enable_step3_soft_enc(void) vlock_reg_get(); vlock_log_cnt++; } + if (vlock_debug & VLOCK_DEBUG_INFO) + pr_info(">>>[%s]\n", __func__); } + /*check pll adj value (0x3020),otherwise may cause blink*/ static void vlock_pll_adj_limit_check(unsigned int *pll_val) { @@ -1092,6 +1104,7 @@ static void vlock_pll_adj_limit_check(unsigned int *pll_val) } } } + static void vlock_enable_step3_pll(void) { unsigned int m_reg_value, tmp_value, abs_val; @@ -2137,16 +2150,16 @@ void vlock_fsm_monitor(struct vframe_s *vf) */ void vlock_process(struct vframe_s *vf) { - if (probe_ok == 0) + if (probe_ok == 0 || !vlock_en) return; if (vlock_debug & VLOCK_DEBUG_FSM_DIS) return; /* todo:vlock processs only for tv chip */ - if (is_meson_gxtvbb_cpu() || - is_meson_txl_cpu() || is_meson_txlx_cpu() - || is_meson_txhd_cpu()) { + if (vlock.dtdata->vlk_new_fsm) + vlock_fsm_monitor(vf); + else { if (vf != NULL) amve_vlock_process(vf); else @@ -2216,6 +2229,7 @@ void vlock_status(void) pr_info("vlock_debug:0x%x\n", vlock_debug); pr_info("vlock_dynamic_adjust:%d\n", vlock_dynamic_adjust); pr_info("vlock_state:%d\n", vlock_state); + pr_info("vecm_latch_flag:0x%x\n", vecm_latch_flag); pr_info("vlock_sync_limit_flag:%d\n", vlock_sync_limit_flag); pr_info("pre_hiu_reg_m:0x%x\n", pre_hiu_reg_m); pr_info("pre_hiu_reg_frac:0x%x\n", pre_hiu_reg_frac); @@ -2296,8 +2310,17 @@ void vlock_reg_dump(void) void vdin_vlock_input_sel(unsigned int type, enum vframe_source_type_e source_type) { + if (vlock.dtdata->vlk_hwver >= vlock_hw_ver2) + return; + /* + *1:fromhdmi rx , + *2:from tv-decoder, + *3:from dvin, + *4:from dvin, + *5:from 2nd bt656 + */ vlock_intput_type = type & VIDTYPE_TYPEMASK; - if ((vlock_intput_type == 0) || + if ((vlock_intput_type == VIDTYPE_PROGRESSIVE) || (vlock_mode & VLOCK_MODE_MANUAL_SOFT_ENC)) return; if (vlock_intput_type == VIDTYPE_INTERLACE_TOP) { @@ -2377,6 +2400,7 @@ void vlock_param_config(struct device_node *node) vlock_mode &= ~VLOCK_MODE_MANUAL_MIX_PLL_ENC; vlock_mode |= VLOCK_MODE_MANUAL_PLL; } + pr_info("param_config vlock_en:%d\n", vlock_en); } int vlock_notify_callback(struct notifier_block *block, unsigned long cmd, @@ -2425,5 +2449,19 @@ int vlock_notify_callback(struct notifier_block *block, unsigned long cmd, return 0; } +static int __init phlock_phase_config(char *str) +{ + unsigned char *ptr = str; + + pr_info("%s: bootargs is %s.\n", __func__, str); + if (strstr(ptr, "1")) + vlock.phlock_percent = 99; + else + vlock.phlock_percent = 40; + + return 0; +} +__setup("video_reverse=", phlock_phase_config); + /*video lock end*/