From fc3de90be47fec5a136ac7fa34dc2e39169d9f8c Mon Sep 17 00:00:00 2001 From: Long Yu Date: Wed, 7 Feb 2018 17:47:08 +0800 Subject: [PATCH] PD#156734: emmc: refixed core phase value for emmc highspeed busmode Change-Id: I33ce650b3ed9dd6eac41b0814679fb660991a738 Signed-off-by: Long Yu --- drivers/amlogic/mmc/aml_sd_emmc_v3.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c index c7857b861bc8..7ddae869f2e2 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c +++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c @@ -241,10 +241,12 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_host *host, clkc->core_phase = 2; pr_info("%s: try set sd/emmc to DDR mode\n", mmc_hostname(host->mmc)); - } else if ((timing == MMC_TIMING_MMC_HS) - && (host->data->chip_type < MMC_CHIP_G12A)) - clkc->core_phase = 3; - else if ((timing == MMC_TIMING_MMC_HS200) + } else if (timing == MMC_TIMING_MMC_HS) { + if (host->data->chip_type < MMC_CHIP_G12A) + clkc->core_phase = 3; + else + clkc->core_phase = 2; + } else if ((timing == MMC_TIMING_MMC_HS200) || ((timing == MMC_TIMING_SD_HS) && aml_card_type_non_sdio(pdata)) || (timing == MMC_TIMING_UHS_SDR104)) {