From fc8a056676083a04bf1669ec325ebb669c5b6e32 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Mon, 12 Aug 2024 14:15:39 +0800 Subject: [PATCH] drm/rockchip: vop2: get the real dclk parent When assign the vp dclk parent as hdmi phy pll in dts. The vp dclk parent should get by clk_get_parent. The vp.dclk_parent is not the real parent. Change-Id: I4b1ba1e1b46e2f5db323069402c4b322ba4a836f Signed-off-by: Zhang Yubing --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 67976c852687..e7fc1c27facd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -8498,8 +8498,8 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) request_clock = request_clock >> 2; } clock = rockchip_drm_dclk_round_rate(vop2->version, - vp->dclk_parent ? vp->dclk_parent : vp->dclk, - request_clock * 1000) / 1000; + vp->dclk_parent ? clk_get_parent(vp->dclk) : + vp->dclk, request_clock * 1000) / 1000; } /* @@ -8925,8 +8925,8 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE) { adj_mode->crtc_clock = rockchip_drm_dclk_round_rate(vop2->version, - vp->dclk_parent ? vp->dclk_parent : vp->dclk, - adj_mode->crtc_clock * 1000); + vp->dclk_parent ? clk_get_parent(vp->dclk) : + vp->dclk, adj_mode->crtc_clock * 1000); adj_mode->crtc_clock = DIV_ROUND_UP(adj_mode->crtc_clock, 1000); } return true;