From fcd70617452f9cb71b7ebca772ab6c050f4a4c37 Mon Sep 17 00:00:00 2001 From: Yun Cai Date: Thu, 9 Feb 2017 19:35:31 +0800 Subject: [PATCH] clocktree: add misc clock PD#138714: add misc clock for gxl Change-Id: I64a0fe72536ec335fa7eff18838a13fbcf99f91e Signed-off-by: Yun Cai --- drivers/amlogic/clk/Makefile | 2 +- drivers/amlogic/clk/clk_misc.c | 102 +++++++++++++++++++ drivers/amlogic/clk/clkc.h | 1 + drivers/amlogic/clk/gxl.c | 1 + drivers/amlogic/clk/gxl.h | 1 + include/dt-bindings/clock/amlogic,gxl-clkc.h | 8 +- 6 files changed, 113 insertions(+), 2 deletions(-) create mode 100644 drivers/amlogic/clk/clk_misc.c diff --git a/drivers/amlogic/clk/Makefile b/drivers/amlogic/clk/Makefile index 2193e201348b..f1272dcd32cd 100644 --- a/drivers/amlogic/clk/Makefile +++ b/drivers/amlogic/clk/Makefile @@ -6,6 +6,6 @@ obj-$(CONFIG_AMLOGIC_RESET) += rstc.o obj-$(CONFIG_AMLOGIC_CLK) += clk-pll.o clk-cpu.o clk-mpll.o \ gxl.o clk_measure.o \ - clk_sdemmc.o clk_gpu.o clk_media.o \ + clk_sdemmc.o clk_gpu.o clk_media.o clk_misc.o\ clk-mux.o obj-$(CONFIG_AMLOGIC_CLK) += clk_test.o diff --git a/drivers/amlogic/clk/clk_misc.c b/drivers/amlogic/clk/clk_misc.c new file mode 100644 index 000000000000..5875bbcb9dfd --- /dev/null +++ b/drivers/amlogic/clk/clk_misc.c @@ -0,0 +1,102 @@ +/* + * drivers/amlogic/clk/clk_misc.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clkc.h" +#include "gxl.h" + +const char *meas_parent_names[] = { "xtal", "fclk_div4", + "fclk_div3", "fclk_div5", "vid_pll_clk", "vid2_pll_clk"}; + +/* cts_vdin_meas_clk */ +static struct clk_mux vdin_meas_mux = { + .reg = (void *)HHI_VDIN_MEAS_CLK_CNTL, + .mask = 0x7, + .shift = 9, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vdin_meas_mux", + .ops = &clk_mux_ops, + .parent_names = meas_parent_names, + .num_parents = 6, + .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_divider vdin_meas_div = { + .reg = (void *)HHI_VDIN_MEAS_CLK_CNTL, + .shift = 0, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vdin_meas_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "vdin_meas_mux" }, + .num_parents = 1, + .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_gate vdin_meas_gate = { + .reg = (void *)HHI_VDIN_MEAS_CLK_CNTL, + .bit_idx = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data) { + .name = "vdin_meas_gate", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "vdin_meas_div" }, + .num_parents = 1, + .flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_hw *vdin_meas_clk_hws[] = { +[CLKID_VDIN_MEAS_MUX - CLKID_VDIN_MEAS_MUX] = &vdin_meas_mux.hw, +[CLKID_VDIN_MEAS_DIV - CLKID_VDIN_MEAS_MUX] = &vdin_meas_div.hw, +[CLKID_VDIN_MEAS_GATE - CLKID_VDIN_MEAS_MUX] = &vdin_meas_gate.hw, +}; + +void amlogic_init_misc(void) +{ + /* cts_vdin_meas_clk */ + vdin_meas_mux.reg = clk_base + (u64)(vdin_meas_mux.reg); + vdin_meas_div.reg = clk_base + (u64)(vdin_meas_div.reg); + vdin_meas_gate.reg = clk_base + (u64)(vdin_meas_gate.reg); + + clks[CLKID_VDIN_MEAS_COMP] = clk_register_composite(NULL, + "vdin_meas_composite", + meas_parent_names, 6, + vdin_meas_clk_hws[CLKID_VDIN_MEAS_MUX - CLKID_VDIN_MEAS_MUX], + &clk_mux_ops, + vdin_meas_clk_hws[CLKID_VDIN_MEAS_DIV - CLKID_VDIN_MEAS_MUX], + &clk_divider_ops, + vdin_meas_clk_hws[CLKID_VDIN_MEAS_GATE - CLKID_VDIN_MEAS_MUX], + &clk_gate_ops, 0); + if (IS_ERR(clks[CLKID_VDIN_MEAS_COMP])) + pr_err("%s: %d clk_register_composite vdin_meas_composite error\n", + __func__, __LINE__); + + pr_info("%s: register meson misc clk\n", __func__); +}; + diff --git a/drivers/amlogic/clk/clkc.h b/drivers/amlogic/clk/clkc.h index e985a0c251e7..c0b38c463ebe 100644 --- a/drivers/amlogic/clk/clkc.h +++ b/drivers/amlogic/clk/clkc.h @@ -132,4 +132,5 @@ extern struct clk **clks; void amlogic_init_sdemmc(void); void amlogic_init_gpu(void); void amlogic_init_media(void); +void amlogic_init_misc(void); #endif /* __CLKC_H */ diff --git a/drivers/amlogic/clk/gxl.c b/drivers/amlogic/clk/gxl.c index c3169a71e2b2..c9f85b7110fd 100644 --- a/drivers/amlogic/clk/gxl.c +++ b/drivers/amlogic/clk/gxl.c @@ -1082,6 +1082,7 @@ static void __init gxl_clkc_init(struct device_node *np) amlogic_init_sdemmc(); amlogic_init_gpu(); amlogic_init_media(); + amlogic_init_misc(); pr_debug("%s: register all clk ok!", __func__); /* * Register CPU clk notifier diff --git a/drivers/amlogic/clk/gxl.h b/drivers/amlogic/clk/gxl.h index 99b376913562..59144b5366f5 100644 --- a/drivers/amlogic/clk/gxl.h +++ b/drivers/amlogic/clk/gxl.h @@ -77,6 +77,7 @@ #define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ #define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 /* 0x94 offset in data sheet */ #define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ #define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ #define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ diff --git a/include/dt-bindings/clock/amlogic,gxl-clkc.h b/include/dt-bindings/clock/amlogic,gxl-clkc.h index b2213242a093..f9bee96df576 100644 --- a/include/dt-bindings/clock/amlogic,gxl-clkc.h +++ b/include/dt-bindings/clock/amlogic,gxl-clkc.h @@ -238,6 +238,12 @@ #define CLKID_VAPB_MUX (CLKID_MEDIA_BASE + 44) #define CLKID_GE2D_GATE (CLKID_MEDIA_BASE + 45) -#define NR_CLKS (OTHER_BASE + 79) +#define CLKID_MISC_BASE (CLKID_MEDIA_BASE + 46) /*25+25+26+18+20+5+24+9+46*/ +#define CLKID_VDIN_MEAS_MUX (CLKID_MISC_BASE + 0) +#define CLKID_VDIN_MEAS_DIV (CLKID_MISC_BASE + 1) +#define CLKID_VDIN_MEAS_GATE (CLKID_MISC_BASE + 2) +#define CLKID_VDIN_MEAS_COMP (CLKID_MISC_BASE + 3) + +#define NR_CLKS (OTHER_BASE + 83) #endif /* __GX_CLKC_H */