From fcf292577e3d60d98998ffef1a33501e56b126ea Mon Sep 17 00:00:00 2001
From: Huang zhibao <hzb@rock-chips.com>
Date: Mon, 22 Nov 2021 15:56:24 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588-nvr-demo: add dp1 support

Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I7604bd230aba201efd09204eb910d5a0c03cead4
---
 .../boot/dts/rockchip/rk3588-nvr-demo.dtsi    | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi
index 90663b704a31..31287a72a963 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi
@@ -151,6 +151,24 @@
 	status = "okay";
 };
 
+&dp1 {
+	pinctrl-0 = <&dp1m2_pins &dp1_hdmi_ctl>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&dp1_in_vp0 {
+	status = "okay";
+};
+
+&dp1_in_vp1 {
+	status = "okay";
+};
+
+&dp1_in_vp2 {
+	status = "okay";
+};
+
 &gmac0 {
 	/* Use rgmii-rxid mode to disable rx delay inside Soc */
 	phy-mode = "rgmii-rxid";
@@ -448,6 +466,13 @@
 };
 
 &pinctrl {
+	dp {
+		dp1_hdmi_ctl: dp-hdmi-ctl {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>,
+					<3 RK_PB2 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
 	rtc {
 		rtc_int: rtc-int {
 			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -540,6 +565,7 @@
 };
 
 &usbdp_phy1 {
+	rockchip,dp-lane-mux = < 0 1 2 3 >;
 	status = "okay";
 };