From fd258c7ba6f32295f49eff57d0d04be85226bee5 Mon Sep 17 00:00:00 2001
From: Wyon Bi <bivvy.bi@rock-chips.com>
Date: Fri, 8 Jan 2021 08:59:45 +0000
Subject: [PATCH] arm64: dts: rockchip: rk3566-evb3-ddr3-v10: Add edp2vga
 bridge support

Change-Id: I8283622639e8be1b9567b7133ec4b614ffc9a85f
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
---
 .../dts/rockchip/rk3566-evb3-ddr3-v10.dtsi    | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi
index 083282293620..748d381f1eca 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi
@@ -21,6 +21,16 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&hp_det>;
 	};
+
+	vcc3v3_vga: vcc3v3-vga {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_vga";
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&vcc3v3_sys>;
+	};
 };
 
 &combphy1_usq {
@@ -73,6 +83,23 @@
 	pinctrl-0 = <&lcd1_rst_gpio>;
 };
 
+&edp {
+	hpd-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&edp_phy {
+	status = "okay";
+};
+
+&edp_in_vp0 {
+	status = "okay";
+};
+
+&edp_in_vp1 {
+	status = "disabled";
+};
+
 &gmac1 {
 	phy-mode = "rgmii";
 	clock_in_out = "output";