From fd54e4d30137ff6be3771cd80c6cf8267e1d049d Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Wed, 16 Sep 2020 16:36:06 +0800 Subject: [PATCH] phy/rockchip: Add driver for Rockchip Naneng eDP Transmitter PHY DPTPHYT22ULP is designed for chips that perform eDP/DP data communication while operating at low power consumption. The main link is a multi-gigabit transmitter macro which enable speed up to 4.0Gbps data transmitter with optimized power and die size, also it can be easily fabricated and implemented in a video system. The AUX channel is a halfduplex, bidirectional channel consisting of one differential pair, supporting the bit rate of about 1Mbps. Macro consists of multi-main link transmitter channels, AUX channel, one PLL and bias-gen unit. The main link transmitter performs dedicated P2S, clock generator, driver with preemphasis and self-test. Each of the channels can be turned off individually. Change-Id: Idf58991ff1bdd4557c4cfadf2dc047e95eca7668 Signed-off-by: Wyon Bi --- drivers/phy/rockchip/Kconfig | 7 +++++++ drivers/phy/rockchip/Makefile | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 04c618d50c83..f9a2c00997e2 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -80,6 +80,13 @@ config PHY_ROCKCHIP_NANENG_COMBO_PHY Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII combo PHY with NaNeng IP block. +config PHY_ROCKCHIP_NANENG_EDP + tristate "Rockchip Naneng eDP Transmitter PHY driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + help + Support for Rockchip eDP Transmitter PHY with Naneng IP block. + config PHY_ROCKCHIP_NANENG_USB2 tristate "Rockchip NANENG USB2PHY Driver" depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index a1b9d4902394..47773188ce0e 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_EDP) += phy-rockchip-naneng-edp.o obj-$(CONFIG_PHY_ROCKCHIP_NANENG_USB2) += phy-rockchip-naneng-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o