diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
index 0b2174ee4ea4..19a45691f3f4 100644
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
@@ -46,7 +46,7 @@
  *
  *
  */
-#define RX_VER2 "ver.2019/01/04"
+#define RX_VER2 "ver.2019/01/10"
 
 /*print type*/
 #define	LOG_EN		0x01
diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
index 485e0cb0c732..9c265952d703 100644
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
@@ -116,8 +116,10 @@ int data;
 unsigned long dev_offset = 0x10;
 
 	if (rx.chip_id == CHIP_ID_TL1) {
+		spin_lock_irqsave(&reg_rw_lock, flags);
 		data = rd_reg(MAP_ADDR_MODULE_TOP,
 			addr + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr);
+		spin_unlock_irqrestore(&reg_rw_lock, flags);
 	} else {
 		spin_lock_irqsave(&reg_rw_lock, flags);
 		wr_reg(MAP_ADDR_MODULE_TOP,
@@ -152,8 +154,10 @@ ulong flags;
 unsigned int dev_offset = 0x10;
 
 	if (rx.chip_id == CHIP_ID_TL1) {
+		spin_lock_irqsave(&reg_rw_lock, flags);
 		wr_reg(MAP_ADDR_MODULE_TOP,
 			addr + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr, data);
+		spin_unlock_irqrestore(&reg_rw_lock, flags);
 	} else {
 		spin_lock_irqsave(&reg_rw_lock, flags);
 		wr_reg(MAP_ADDR_MODULE_TOP,
@@ -284,6 +288,7 @@ unsigned int hdmirx_rd_top(unsigned int addr)
 	unsigned int tempaddr = 0;
 
 	if (rx.chip_id == CHIP_ID_TL1) {
+		spin_lock_irqsave(&reg_rw_lock, flags);
 		dev_offset = TOP_DWC_BASE_OFFSET +
 			reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
 		if ((addr >= TOP_EDID_OFFSET) &&
@@ -296,6 +301,7 @@ unsigned int hdmirx_rd_top(unsigned int addr)
 			data = rd_reg(MAP_ADDR_MODULE_TOP,
 				dev_offset + (addr<<2));
 		}
+		spin_unlock_irqrestore(&reg_rw_lock, flags);
 	} else {
 		data = rd_reg(MAP_ADDR_MODULE_TOP,
 			dev_offset + (addr<<2));
@@ -335,6 +341,7 @@ void hdmirx_wr_top(unsigned int addr, unsigned int data)
 	unsigned int tempaddr = 0;
 
 	if (rx.chip_id == CHIP_ID_TL1) {
+		spin_lock_irqsave(&reg_rw_lock, flags);
 		dev_offset = TOP_DWC_BASE_OFFSET +
 			reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
 		if ((addr >= TOP_EDID_OFFSET) &&
@@ -347,6 +354,7 @@ void hdmirx_wr_top(unsigned int addr, unsigned int data)
 			wr_reg(MAP_ADDR_MODULE_TOP,
 				dev_offset + (addr<<2), data);
 		}
+		spin_unlock_irqrestore(&reg_rw_lock, flags);
 	} else {
 		wr_reg(MAP_ADDR_MODULE_TOP,
 			dev_offset + (addr<<2), data);
@@ -381,10 +389,16 @@ hdmirx_wr_top(addr, rx_set_bits(hdmirx_rd_top(addr), mask, value));
 */
 unsigned int rd_reg_hhi(unsigned int offset)
 {
-unsigned int addr = offset +
-	reg_maps[MAP_ADDR_MODULE_HIU].phy_addr;
+	unsigned int ret;
+	unsigned long flags;
+	unsigned int addr;
 
-return rd_reg(MAP_ADDR_MODULE_HIU, addr);
+	spin_lock_irqsave(&reg_rw_lock, flags);
+	addr = offset +
+		reg_maps[MAP_ADDR_MODULE_HIU].phy_addr;
+	ret = rd_reg(MAP_ADDR_MODULE_HIU, addr);
+	spin_unlock_irqrestore(&reg_rw_lock, flags);
+	return ret;
 }
 
 /*
@@ -406,9 +420,14 @@ unsigned int rd_reg_hhi_bits(unsigned int offset, unsigned int mask)
  */
 void wr_reg_hhi(unsigned int offset, unsigned int val)
 {
-unsigned int addr = offset +
-	reg_maps[MAP_ADDR_MODULE_HIU].phy_addr;
-wr_reg(MAP_ADDR_MODULE_HIU, addr, val);
+	unsigned long flags;
+	unsigned int addr;
+
+	spin_lock_irqsave(&reg_rw_lock, flags);
+	addr = offset +
+		reg_maps[MAP_ADDR_MODULE_HIU].phy_addr;
+	wr_reg(MAP_ADDR_MODULE_HIU, addr, val);
+	spin_unlock_irqrestore(&reg_rw_lock, flags);
 }
 
 /*
@@ -714,14 +733,17 @@ void hdmirx_wr_ctl_port(unsigned int offset, unsigned int data)
 */
 void hdmirx_top_sw_reset(void)
 {
-ulong flags;
-unsigned long dev_offset = 0;
-
+	ulong flags;
+	unsigned long dev_offset = 0;
 	spin_lock_irqsave(&reg_rw_lock, flags);
 	if (rx.chip_id == CHIP_ID_TL1) {
-		hdmirx_wr_top(TOP_SW_RESET, 1);
+		dev_offset = TOP_DWC_BASE_OFFSET +
+			reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
+		wr_reg(MAP_ADDR_MODULE_TOP,
+			dev_offset + TOP_SW_RESET, 1);
 		udelay(1);
-		hdmirx_wr_top(TOP_SW_RESET, 0);
+		wr_reg(MAP_ADDR_MODULE_TOP,
+			dev_offset + TOP_SW_RESET, 0);
 	} else {
 		wr_reg(MAP_ADDR_MODULE_TOP,
 			hdmirx_addr_port | dev_offset, TOP_SW_RESET);