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mmc: rk_sdmmc: fix compile warning

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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Shawn Lin
2015-05-22 18:17:48 +08:00
parent 6e719a67ff
commit fd75a4d1d5
2 changed files with 46 additions and 44 deletions
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46
drivers/mmc/host/rk_sdmmc.c
View File

@@ -138,6 +138,52 @@ static const u8 tuning_blk_pattern_8bit[] = {
0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
};
static struct sdmmc_reg dw_mci_regs[] =
{
{ 0x0000, "CTRL" },
{ 0x0004, "PWREN" },
{ 0x0008, "CLKDIV" },
{ 0x000C, "CLKSRC" },
{ 0x0010, "CLKENA" },
{ 0x0014, "TMOUT" },
{ 0x0018, "CTYPE" },
{ 0x001C, "BLKSIZ" },
{ 0x0020, "BYTCNT" },
{ 0x0024, "INTMASK" },
{ 0x0028, "CMDARG" },
{ 0x002C, "CMD" },
{ 0x0030, "RESP0" },
{ 0x0034, "RESP1" },
{ 0x0038, "RESP2" },
{ 0x003C, "RESP3" },
{ 0x0040, "MINSTS" },
{ 0x0044, "RINTSTS" },
{ 0x0048, "STATUS" },
{ 0x004C, "FIFOTH" },
{ 0x0050, "CDETECT" },
{ 0x0054, "WRTPRT" },
{ 0x0058, "GPIO" },
{ 0x005C, "TCBCNT" },
{ 0x0060, "TBBCNT" },
{ 0x0064, "DEBNCE" },
{ 0x0068, "USRID" },
{ 0x006C, "VERID" },
{ 0x0070, "HCON" },
{ 0x0074, "UHS_REG" },
{ 0x0078, "RST_n" },
{ 0x0080, "BMOD" },
{ 0x0084, "PLDMND" },
{ 0x0088, "DBADDR" },
{ 0x008C, "IDSTS" },
{ 0x0090, "IDINTEN" },
{ 0x0094, "DSCADDR" },
{ 0x0098, "BUFADDR" },
{ 0x0100, "CARDTHRCTL" },
{ 0x0104, "BackEndPwr" },
{ 0, 0 }
};
static inline bool dw_mci_fifo_reset(struct dw_mci *host);
static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);

44
drivers/mmc/host/rk_sdmmc.h
View File

@@ -77,50 +77,6 @@ u32 addr;
char *name;
};
static struct sdmmc_reg dw_mci_regs[] =
{
{ 0x0000, "CTRL" },
{ 0x0004, "PWREN" },
{ 0x0008, "CLKDIV" },
{ 0x000C, "CLKSRC" },
{ 0x0010, "CLKENA" },
{ 0x0014, "TMOUT" },
{ 0x0018, "CTYPE" },
{ 0x001C, "BLKSIZ" },
{ 0x0020, "BYTCNT" },
{ 0x0024, "INTMASK" },
{ 0x0028, "CMDARG" },
{ 0x002C, "CMD" },
{ 0x0030, "RESP0" },
{ 0x0034, "RESP1" },
{ 0x0038, "RESP2" },
{ 0x003C, "RESP3" },
{ 0x0040, "MINSTS" },
{ 0x0044, "RINTSTS" },
{ 0x0048, "STATUS" },
{ 0x004C, "FIFOTH" },
{ 0x0050, "CDETECT" },
{ 0x0054, "WRTPRT" },
{ 0x0058, "GPIO" },
{ 0x005C, "TCBCNT" },
{ 0x0060, "TBBCNT" },
{ 0x0064, "DEBNCE" },
{ 0x0068, "USRID" },
{ 0x006C, "VERID" },
{ 0x0070, "HCON" },
{ 0x0074, "UHS_REG" },
{ 0x0078, "RST_n" },
{ 0x0080, "BMOD" },
{ 0x0084, "PLDMND" },
{ 0x0088, "DBADDR" },
{ 0x008C, "IDSTS" },
{ 0x0090, "IDINTEN" },
{ 0x0094, "DSCADDR" },
{ 0x0098, "BUFADDR" },
{ 0x0100, "CARDTHRCTL" },
{ 0x0104, "BackEndPwr" },
{ 0, 0 }
};
/* Control register defines */
#define SDMMC_CTRL_USE_IDMAC BIT(25)