From fda420801320d18b87a64fe7963308f9a1235e21 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Tue, 23 Feb 2021 10:00:30 +0800 Subject: [PATCH] drivers: rkflash: Support new spiflash 1.spinand: MX35UF1GE4AC, MX35UF2GE4AC, GD5F4GQ6RExxG, GD5F4GQ6UExxG, XT26G01C, XT26G04C, BWJX08K-2Gb, XT26G02C 2.spinor: GD25Q128E, GD25Q256E, GD25Q256B, GD25LQ32E, GD25LQ32E, W25Q32JW, MX25U3232F, MX25U6432F, MX25U12832F, MX25U25645GZ4I,, XT25F32BS, XT25F16BS, P25Q64H, P25Q128H, P25Q16H, FM25Q64A, FM25M64C, FM25M4AA, DS25M4AB Change-Id: If2259456e9cc01281cd4e11a6d3338f2a0402357 Signed-off-by: Jon Lin --- drivers/rkflash/sfc_nand.c | 78 +++++++++++++++++++++++++++++++++----- drivers/rkflash/sfc_nor.c | 50 ++++++++++++++++++++---- 2 files changed, 111 insertions(+), 17 deletions(-) diff --git a/drivers/rkflash/sfc_nand.c b/drivers/rkflash/sfc_nand.c index 612ab2545be7..9e61d3d76ac8 100644 --- a/drivers/rkflash/sfc_nand.c +++ b/drivers/rkflash/sfc_nand.c @@ -18,6 +18,7 @@ static u32 sfc_nand_get_ecc_status3(void); static u32 sfc_nand_get_ecc_status4(void); static u32 sfc_nand_get_ecc_status5(void); static u32 sfc_nand_get_ecc_status6(void); +static u32 sfc_nand_get_ecc_status7(void); static struct nand_info spi_nand_tbl[] = { /* TC58CVG0S0HxAIx */ @@ -38,9 +39,11 @@ static struct nand_info spi_nand_tbl[] = { /* MX35LF2GE4AD */ { 0xC2, 0x26, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, /* MX35LF4GE4AD */ - { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, - /* MT29F1G01ZAC */ - { 0x2C, 0x12, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, + /* MX35UF1GE4AC */ + { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, + /* MX35UF2GE4AC */ + { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, /* GD5F1GQ4UAYIG */ { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, @@ -54,6 +57,10 @@ static struct nand_info spi_nand_tbl[] = { { 0xC8, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, /* GD5F1GQ4R */ { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, + /* GD5F4GQ6RExxG 1*4096 */ + { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, + /* GD5F4GQ6UExxG 1*4096 */ + { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, /* W25N01GV */ { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, @@ -101,17 +108,23 @@ static struct nand_info spi_nand_tbl[] = { { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, /* XT26G02A */ - { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, + { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, /* XT26G01A */ - { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, + { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, /* XT26G04A */ - { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, + { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, /* XT26G01B */ - { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, + { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, /* XT26G02B */ - { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, + { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, + /* XT26G01C */ + { 0x0B, 0x11, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, + /* XT26G02C */ + { 0x0B, 0x12, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, + /* XT26G04C */ + { 0x0B, 0x13, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status7 }, - /* MT29F2G1ABA, XT26G02E, F50L2G41XA */ + /* MT29F2G01ABA, XT26G02E, F50L2G41XA */ { 0x2C, 0x24, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, /* FM25S01 */ @@ -127,6 +140,8 @@ static struct nand_info spi_nand_tbl[] = { { 0xC8, 0x01, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, /* ATO25D1GA */ { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + /* BWJX08K-2Gb */ + { 0xBC, 0xB3, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x04, 0x10, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, }; static struct nand_info *p_nand_info; @@ -260,7 +275,7 @@ static int sfc_nand_wait_busy(u8 *data, int timeout) * 0b01, Bit errors were detected and corrected. * 0b10, Multiple bit errors were detected and not corrected. * 0b11, Bits errors were detected and corrected, bit error count - * exceed the bit flip detection threshold + * reach the bit flip detection threshold */ static u32 sfc_nand_get_ecc_status0(void) { @@ -566,6 +581,49 @@ static u32 sfc_nand_get_ecc_status6(void) return ret; } +/* + * ecc spectial type7: + * ecc bits: 0xC0[4,7] + * [0b0000], No bit errors were detected; + * [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not + * reach Flipping Bits; + * [0b1000], 8 Bit errors were detected and corrected. Bit error count + * equals the bit flip detectionthreshold; + * [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected; + * others, Reserved. + */ +static u32 sfc_nand_get_ecc_status7(void) +{ + u32 ret; + u32 i; + u8 ecc; + u8 status; + u32 timeout = 1000 * 1000; + + for (i = 0; i < timeout; i++) { + ret = sfc_nand_read_feature(0xC0, &status); + + if (ret != SFC_OK) + return SFC_NAND_ECC_ERROR; + + if (!(status & (1 << 0))) + break; + + sfc_delay(1); + } + + ecc = (status >> 4) & 0xf; + + if (ecc < 7) + ret = SFC_NAND_ECC_OK; + else if (ecc == 7 || ecc == 8) + ret = SFC_NAND_ECC_REFRESH; + else + ret = (u32)SFC_NAND_ECC_ERROR; + + return ret; +} + u32 sfc_nand_erase_block(u8 cs, u32 addr) { int ret; diff --git a/drivers/rkflash/sfc_nor.c b/drivers/rkflash/sfc_nor.c index 788f6e380a84..f7abe75a5b09 100644 --- a/drivers/rkflash/sfc_nor.c +++ b/drivers/rkflash/sfc_nor.c @@ -15,21 +15,29 @@ static struct flash_info spi_flash_tbl[] = { { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, /* GD25Q64B */ { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, - /* GD25Q127C and GD25Q128C*/ + /* GD25Q127C and GD25Q128C/E */ { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, - /* GD25Q256B/C/D */ + /* GD25Q256B/C/D/E */ { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, /* GD25Q512MC */ - { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 17, 6, 0 }, + { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 }, + /* GD25LQ64C */ + { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, + /* GD25LQ32E */ + { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, /* GD25B512MEYIG */ - { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 17, 0, 0 }, + { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 }, + /* W25Q32JV */ + { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, /* W25Q64JVSSIQ */ { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, /* W25Q128FV and W25Q128JV*/ { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, /* W25Q256F/J */ { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, + /* W25Q32JW */ + { 0xef6016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, /* W25Q256JWEQ*/ { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, /* W25Q64FWSSIG */ @@ -45,12 +53,20 @@ static struct flash_info spi_flash_tbl[] = { { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, /* MX25L12835E/F MX25L12833FMI-10G */ { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, - /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G*/ - { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 16, 6, 0 }, + /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G */ + { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, /* MX25L51245GMI */ - { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 17, 6, 0 }, + { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, /* MX25U51245G */ { 0xc2253a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, + /* MX25U3232F */ + { 0xc22536, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 13, 6, 0 }, + /* MX25U6432F */ + { 0xc22537, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 14, 6, 0 }, + /* MX25U12832F */ + { 0xc22538, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 15, 6, 0 }, + /* MX25U25645GZ4I-00 */ + { 0xc22539, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, /* XM25QH32C */ { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, @@ -71,6 +87,10 @@ static struct flash_info spi_flash_tbl[] = { { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, /* XT25F256BSFIGU */ { 0x0b4019, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 16, 9, 0 }, + /* XT25F32BS */ + { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, + /* XT25F16BS */ + { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, /* EN25QH64A */ { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, @@ -85,6 +105,17 @@ static struct flash_info spi_flash_tbl[] = { /* EN25QH256A */ { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, + /* P25Q64H */ + { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + /* P25Q128H */ + { 0x856018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, + /* P25Q16H-SUH-IT */ + { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, + /* FM25Q64A */ + { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, + /* FM25M64C */ + { 0xf84317, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, + /* ZB25VQ64 */ { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, /* ZB25VQ128 */ @@ -96,6 +127,7 @@ static struct flash_info spi_flash_tbl[] = { { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, /* BH25Q64BS */ { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + /* P25Q64H */ { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, /* P25Q32SH-SSH-IT */ @@ -108,6 +140,10 @@ static struct flash_info spi_flash_tbl[] = { /* FM25Q64A */ { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, + /* FM25M4AA */ + { 0xf84218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, + /* DS25M4AB-1AIB4 */ + { 0xe54218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, }; static int snor_write_en(void)