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PCI: rockchip: fix rk3399 suspend issue

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When RK3399 work as a host connect to RK1808 work as a ep:

1. RK3399 pcie DO NOT enter L2 state when suspend, because RK1808 won't
   send the ACK.
2. Hand the link operation to userspace when RK3399 resume
3. Before RK1808 suspend or reboot, RK3399 do following first to break
   the link:

   echo 0x2 > sys/devices/platform/f8000000.pcie/pcie_reset_ep

4. After RK1808 resumed or booted, RK3399 do following to restart
   the link:

   echo 0x1 > sys/devices/platform/f8000000.pcie/pcie_reset_ep

Change-Id: Idc94ab4d2f123744c80ad34a57e1036fec9c53f2
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Signed-off-by: Simon Xue <xxm@rock-chips.com>
This commit is contained in:
Weixin Zhou
2019-07-03 14:49:27 +08:00
committed by Tao Huang
parent 9eae80e2fe
commit fdcb124e09
1 changed files with 17 additions and 0 deletions
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17
drivers/pci/host/pcie-rockchip.c
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@@ -215,6 +215,9 @@
#define RC_REGION_0_PASS_BITS (25 - 1)
#define MAX_AXI_WRAPPER_REGION_NUM 33
#define PCIE_USER_RELINK 0x1
#define PCIE_USER_UNLINK 0x2
struct rockchip_pcie {
void __iomem *reg_base; /* DT axi-base */
void __iomem *apb_base; /* DT apb-base */
@@ -1324,6 +1327,10 @@ static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip)
u32 value;
int err;
/* Don't enter L2 state when no ep connected */
if (rockchip->dma_trx_enabled == 1)
return 0;
/* send PME_TURN_OFF message */
writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
@@ -1376,6 +1383,11 @@ static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev)
clk_prepare_enable(rockchip->aclk_perf_pcie);
clk_prepare_enable(rockchip->aclk_pcie);
if (rockchip->dma_trx_enabled == 1) {
dev_info(dev, "bypass for user to link...");
return 0;
}
err = rockchip_pcie_init_port(rockchip);
if (err)
return err;
@@ -1459,10 +1471,15 @@ static ssize_t pcie_reset_ep_store(struct device *dev,
if (err)
return err;
/* Clear ltssm status before unlinking */
if (val) {
rockchip_pcie_write(rockchip, 0x00020000, PCIE_CLIENT_CONFIG);
phy_power_off(rockchip->phy);
phy_exit(rockchip->phy);
if (val == PCIE_USER_UNLINK)
return size;
rockchip->wait_ep = 1;
err = rockchip_pcie_init_port(rockchip);