From fde6251d1fbefa6441ea8b10706136fb8c445d7a Mon Sep 17 00:00:00 2001 From: David Brazdil Date: Thu, 21 Apr 2022 10:56:36 +0100 Subject: [PATCH] ANDROID: KVM: arm64: s2mpu: Allow r/o access to control regs To ease debugging, allow the host to read the state of S2MPU's control registers. These values do not need to be kept secret from the host. Bug: 190463801 Signed-off-by: David Brazdil Change-Id: Ib9e5be443f38a0ae8fb0d4f5820017d728adf64b --- arch/arm64/include/asm/kvm_s2mpu.h | 15 +++++++++++++++ arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c | 7 +++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm64/include/asm/kvm_s2mpu.h b/arch/arm64/include/asm/kvm_s2mpu.h index d8c552da273f..b1075abd604c 100644 --- a/arch/arm64/include/asm/kvm_s2mpu.h +++ b/arch/arm64/include/asm/kvm_s2mpu.h @@ -51,15 +51,30 @@ #define CTRL0_INTERRUPT_ENABLE BIT(1) #define CTRL0_FAULT_RESP_TYPE_SLVERR BIT(2) /* for v8 */ #define CTRL0_FAULT_RESP_TYPE_DECERR BIT(2) /* for v9 */ +#define CTRL0_MASK (CTRL0_ENABLE | \ + CTRL0_INTERRUPT_ENABLE | \ + CTRL0_FAULT_RESP_TYPE_SLVERR | \ + CTRL0_FAULT_RESP_TYPE_DECERR) #define CTRL1_DISABLE_CHK_S1L1PTW BIT(0) #define CTRL1_DISABLE_CHK_S1L2PTW BIT(1) #define CTRL1_ENABLE_PAGE_SIZE_AWARENESS BIT(2) #define CTRL1_DISABLE_CHK_USER_MATCHED_REQ BIT(3) +#define CTRL1_MASK (CTRL1_DISABLE_CHK_S1L1PTW | \ + CTRL1_DISABLE_CHK_S1L2PTW | \ + CTRL1_ENABLE_PAGE_SIZE_AWARENESS | \ + CTRL1_DISABLE_CHK_USER_MATCHED_REQ) #define CFG_MPTW_CACHE_OVERRIDE BIT(0) +#define CFG_MPTW_CACHE_VALUE GENMASK(7, 4) #define CFG_MPTW_QOS_OVERRIDE BIT(8) +#define CFG_MPTW_QOS_VALUE GENMASK(15, 12) #define CFG_MPTW_SHAREABLE BIT(16) +#define CFG_MASK (CFG_MPTW_CACHE_OVERRIDE | \ + CFG_MPTW_CACHE_VALUE | \ + CFG_MPTW_QOS_OVERRIDE | \ + CFG_MPTW_QOS_VALUE | \ + CFG_MPTW_SHAREABLE) /* For use with hi_lo_readq_relaxed(). */ #define REG_NS_FAULT_PA_HIGH_LOW(vid) REG_NS_FAULT_PA_LOW(vid) diff --git a/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c b/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c index 50f842a3b0de..ff5d7d1044e5 100644 --- a/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c +++ b/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c @@ -394,6 +394,13 @@ static u32 host_mmio_reg_access_mask(size_t off, bool is_write) u32 masked_off; switch (off) { + /* Allow reading control registers for debugging. */ + case REG_NS_CTRL0: + return read_only & CTRL0_MASK; + case REG_NS_CTRL1: + return read_only & CTRL1_MASK; + case REG_NS_CFG: + return read_only & CFG_MASK; /* Allow EL1 IRQ handler to clear interrupts. */ case REG_NS_INTERRUPT_CLEAR: return write_only & ALL_VIDS_BITMAP;