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arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes

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[ Upstream commit 188ffcd7fea79af3cac441268fc99f60e87f03b3 ]

In order to generalize the node names, the DMA-related nodes
corresponding to MT8183 MDP3 need to be corrected.

Fixes: 60a2fb8d20 ("arm64: dts: mt8183: add MediaTek MDP3 nodes")
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Moudy Ho
2023-10-30 17:48:38 +08:00
committed by Greg Kroah-Hartman
parent 9c91f58498
commit fe002eeda4
1 changed files with 4 additions and 2 deletions
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6
arch/arm64/boot/dts/mediatek/mt8183.dtsi
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@@ -1586,7 +1586,7 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
}; };
mdp3-rdma0@14001000 { dma-controller0@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma"; compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0 0x14001000 0 0x1000>; reg = <0 0x14001000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
@@ -1598,6 +1598,7 @@
iommus = <&iommu M4U_PORT_MDP_RDMA0>; iommus = <&iommu M4U_PORT_MDP_RDMA0>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
<&gce 21 CMDQ_THR_PRIO_LOWEST 0>; <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
#dma-cells = <1>;
}; };
mdp3-rsz0@14003000 { mdp3-rsz0@14003000 {
@@ -1618,7 +1619,7 @@
clocks = <&mmsys CLK_MM_MDP_RSZ1>; clocks = <&mmsys CLK_MM_MDP_RSZ1>;
}; };
mdp3-wrot0@14005000 { dma-controller@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot"; compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0 0x14005000 0 0x1000>; reg = <0 0x14005000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
@@ -1627,6 +1628,7 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>; clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu M4U_PORT_MDP_WROT0>; iommus = <&iommu M4U_PORT_MDP_WROT0>;
#dma-cells = <1>;
}; };
mdp3-wdma@14006000 { mdp3-wdma@14006000 {