From fe9341a608c276d9eb61af5870e2642707ca76ff Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 7 Jul 2021 11:52:24 +0800 Subject: [PATCH] drm/rockchip: dsi: add dphy timing for possible external dphy Signed-off-by: Guochun Huang Change-Id: I94e16fe908558edeb0919b64621f7a8c1c58c6a4 --- drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 0d45d1bf1897..eeb6204a9195 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -698,12 +698,25 @@ struct hstt hstt_table[] = { HSTT(1500, 181, 66, 153, 50) }; +struct dw_mipi_dsi_dphy_timing ext_dphy_timing = { + .clk_lp2hs = 0x40, + .clk_hs2lp = 0x40, + .data_lp2hs = 0x10, + .data_hs2lp = 0x14, +}; + static int dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, struct dw_mipi_dsi_dphy_timing *timing) { + struct dw_mipi_dsi_rockchip *dsi = priv_data; int i; + if (dsi->phy) { + *timing = ext_dphy_timing; + return 0; + } + for (i = 0; i < ARRAY_SIZE(hstt_table); i++) if (lane_mbps < hstt_table[i].maxfreq) break;