From fecf3d2a6c719cc4d35a286443402b74659a07b5 Mon Sep 17 00:00:00 2001
From: Huang zhibao <hzb@rock-chips.com>
Date: Fri, 22 Jul 2022 08:58:53 +0800
Subject: [PATCH] ARM: dts: rockchip: rv1106-uvc: Enable clk compensation for
 i2s0

Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I4e87859483fe4494a4e3dc2336e89b9ef9ea65da
---
 arch/arm/boot/dts/rv1106-uvc.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/rv1106-uvc.dtsi b/arch/arm/boot/dts/rv1106-uvc.dtsi
index f6f4e01feec8..cf9404b6fe99 100644
--- a/arch/arm/boot/dts/rv1106-uvc.dtsi
+++ b/arch/arm/boot/dts/rv1106-uvc.dtsi
@@ -41,6 +41,13 @@
 
 &i2s0_8ch {
 	status = "okay";
+	clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>,
+		 <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>,
+		 <&cru PLL_GPLL>, <&cru PLL_GPLL>;
+	clock-names = "mclk_tx", "mclk_rx", "hclk",
+		      "mclk_tx_src", "mclk_rx_src",
+		      "mclk_root0", "mclk_root1";
+	rockchip,mclk-calibrate;
 };
 
 &mpp_srv {