From ff0bc31061e627d4532a26c1563b2dc672747ef3 Mon Sep 17 00:00:00 2001 From: Huang zhibao Date: Wed, 30 Mar 2022 16:30:46 +0800 Subject: [PATCH] ARM: dts: rockchip: add dts for rv1106 uvc demo board Signed-off-by: Huang zhibao Change-Id: Ida1820188cb5b293f5a9a6dda7b1da88193bd895 --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/rv1106-uvc-demo.dtsi | 64 ++++++++++++++++++ arch/arm/boot/dts/rv1106-uvc.dtsi | 66 +++++++++++++++++++ .../boot/dts/rv1106g-uvc-demo-v10-spi-nor.dts | 52 +++++++++++++++ arch/arm/boot/dts/rv1106g-uvc-demo-v10.dts | 16 +++++ 5 files changed, 200 insertions(+) create mode 100644 arch/arm/boot/dts/rv1106-uvc-demo.dtsi create mode 100644 arch/arm/boot/dts/rv1106-uvc.dtsi create mode 100644 arch/arm/boot/dts/rv1106g-uvc-demo-v10-spi-nor.dts create mode 100644 arch/arm/boot/dts/rv1106g-uvc-demo-v10.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f7db9e264a4c..608f95a52341 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -978,6 +978,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1106g-evb1-v10-spi-nand.dtb \ rv1106g-evb1-v10-spi-nor.dtb \ rv1106g-evb2-v10.dtb \ + rv1106g-uvc-demo-v10.dtb \ + rv1106g-uvc-demo-v10-spi-nor.dtb \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb \ rk3036-evb.dtb \ diff --git a/arch/arm/boot/dts/rv1106-uvc-demo.dtsi b/arch/arm/boot/dts/rv1106-uvc-demo.dtsi new file mode 100644 index 000000000000..4083a5c870bc --- /dev/null +++ b/arch/arm/boot/dts/rv1106-uvc-demo.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include "rv1106-uvc.dtsi" +#include "rv1106-evb-cam.dtsi" + +/ { + chosen { + bootargs = "clk_gate.always_on=1 earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 root=/dev/mmcblk0p5 rootfstype=ext4 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16"; + }; + + acodec_sound: acodec-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rv1106-acodec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&acodec>; + }; + }; + + vdd_arm: vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <724000>; + regulator-max-microvolt = <1078000>; + regulator-init-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + }; +}; + +&acodec { + #sound-dai-cells = <0>; + //pa-ctl-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + mmc-hs200-1_8v; + rockchip,default-sample-phase = <90>; + no-sdio; + no-sd; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/rv1106-uvc.dtsi b/arch/arm/boot/dts/rv1106-uvc.dtsi new file mode 100644 index 000000000000..c0984c2d3977 --- /dev/null +++ b/arch/arm/boot/dts/rv1106-uvc.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +/ { + +}; + +&fiq_debugger { + rockchip,irq-mode-enable = <1>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&mpp_vcodec { + status = "okay"; +}; + +&npu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_pp { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&rve { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usbdrd { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rv1106g-uvc-demo-v10-spi-nor.dts b/arch/arm/boot/dts/rv1106g-uvc-demo-v10-spi-nor.dts new file mode 100644 index 000000000000..810af0293a00 --- /dev/null +++ b/arch/arm/boot/dts/rv1106g-uvc-demo-v10-spi-nor.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1106.dtsi" +#include "rv1106-uvc-demo.dtsi" + +/ { + model = "Rockchip RV1106 UVC SPI-NOR V10 Board"; + compatible = "rockchip,rv1106-uvc-nor-demo", "rockchip,rv1106"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16"; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&emmc { + status = "disabled"; +}; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/arch/arm/boot/dts/rv1106g-uvc-demo-v10.dts b/arch/arm/boot/dts/rv1106g-uvc-demo-v10.dts new file mode 100644 index 000000000000..9e9233414068 --- /dev/null +++ b/arch/arm/boot/dts/rv1106g-uvc-demo-v10.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1106.dtsi" +#include "rv1106-uvc-demo.dtsi" + +/ { + model = "Rockchip RV1106 UVC EMMC V10 Board"; + compatible = "rockchip,rv1106-uvc-demo", "rockchip,rv1106"; +}; + +