From ff106652d9b5a2189a9c7db9a939cbfaf8f5ac8b Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 28 Mar 2019 14:37:04 +0800 Subject: [PATCH] clk: rockchip: rk3288: Add 420MHz for PLL Change-Id: Ic722bdf5d467a64cdf093f8bdabb6dab533cd230 Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-rk3288.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 433f72f896ae..ee0e059f8f1f 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -93,6 +93,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 500000000, 3, 125, 2), RK3066_PLL_RATE( 456000000, 1, 76, 4), + RK3066_PLL_RATE( 420000000, 1, 70, 4), RK3066_PLL_RATE( 408000000, 1, 68, 4), RK3066_PLL_RATE( 400000000, 3, 100, 2), RK3066_PLL_RATE( 384000000, 2, 128, 4),