From ff311139ed5a97b07ccb837fb86d031002a2cddc Mon Sep 17 00:00:00 2001
From: Damon Ding <damon.ding@rock-chips.com>
Date: Thu, 10 Nov 2022 18:47:40 +0800
Subject: [PATCH] ARM: dts: rockchip: rk3288: remove PLL_CPLL assignment from
 cru node

PLL_CPLL is for VOP only, which does not need to be
initialized in CRU.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ic51b4e2ef377ee6f796e807131f1fe02d0db39cc
---
 arch/arm/boot/dts/rk3288.dtsi | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 078c151ee854..1a9bb2c59dfb 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -893,16 +893,14 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
-		assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
-				  <&cru PLL_NPLL>, <&cru ACLK_CPU>,
-				  <&cru HCLK_CPU>, <&cru PCLK_CPU>,
-				  <&cru ACLK_PERI>, <&cru HCLK_PERI>,
-				  <&cru PCLK_PERI>;
-		assigned-clock-rates = <594000000>, <400000000>,
-				       <500000000>, <300000000>,
-				       <150000000>, <75000000>,
+		assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_NPLL>,
+				  <&cru ACLK_CPU>, <&cru HCLK_CPU>,
+				  <&cru PCLK_CPU>, <&cru ACLK_PERI>,
+				  <&cru HCLK_PERI>, <&cru PCLK_PERI>;
+		assigned-clock-rates = <594000000>, <500000000>,
 				       <300000000>, <150000000>,
-				       <75000000>;
+				       <75000000>, <300000000>,
+				       <150000000>, <75000000>;
 	};
 
 	grf: syscon@ff770000 {