From ffb82a0e28b78da557e4a27a03bb49f3b196973b Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Tue, 28 Jul 2020 15:49:52 +0800 Subject: [PATCH] soc: rockchip: cpuinfo: Add support for cpu code parse This patch add cpu code parse from otp or efuse. Signed-off-by: Sugar Zhang Change-Id: I550eb01725ba265d5eb47caaf1d0e66656cfb4b0 --- drivers/soc/rockchip/rockchip-cpuinfo.c | 11 +++++++++++ include/linux/rockchip/cpu.h | 22 +++++++++++++++++----- 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/soc/rockchip/rockchip-cpuinfo.c b/drivers/soc/rockchip/rockchip-cpuinfo.c index faea58a09eed..907eaa788485 100644 --- a/drivers/soc/rockchip/rockchip-cpuinfo.c +++ b/drivers/soc/rockchip/rockchip-cpuinfo.c @@ -32,6 +32,16 @@ static int rockchip_cpuinfo_probe(struct platform_device *pdev) size_t len; int i; + cell = nvmem_cell_get(dev, "cpu-code"); + if (!IS_ERR(cell)) { + efuse_buf = nvmem_cell_read(cell, &len); + nvmem_cell_put(cell); + + if (len == 2) + rockchip_set_cpu((efuse_buf[0] << 8 | efuse_buf[1])); + kfree(efuse_buf); + } + cell = nvmem_cell_get(dev, "cpu-version"); if (!IS_ERR(cell)) { efuse_buf = nvmem_cell_read(cell, &len); @@ -68,6 +78,7 @@ static int rockchip_cpuinfo_probe(struct platform_device *pdev) system_serial_low = crc32(0, buf, 8); system_serial_high = crc32(system_serial_low, buf + 8, 8); + dev_info(dev, "SoC\t\t: %lx\n", rockchip_soc_id); dev_info(dev, "Serial\t\t: %08x%08x\n", system_serial_high, system_serial_low); diff --git a/include/linux/rockchip/cpu.h b/include/linux/rockchip/cpu.h index 554299351875..e1b4a558c155 100644 --- a/include/linux/rockchip/cpu.h +++ b/include/linux/rockchip/cpu.h @@ -16,6 +16,12 @@ #include +#define ROCKCHIP_CPU_MASK 0xffff0000 +#define ROCKCHIP_CPU_SHIFT 16 +#define ROCKCHIP_CPU_RK312X 0x31260000 +#define ROCKCHIP_CPU_RK3288 0x32880000 +#define ROCKCHIP_CPU_RK3308 0x33080000 + #ifdef CONFIG_ROCKCHIP_CPUINFO extern unsigned long rockchip_soc_id; @@ -36,6 +42,14 @@ static inline void rockchip_set_cpu_version(unsigned long ver) (ver << ROCKCHIP_CPU_VERION_SHIFT) & ROCKCHIP_CPU_VERION_MASK; } +static inline void rockchip_set_cpu(unsigned long code) +{ + if (!code) + return; + + rockchip_soc_id &= ~ROCKCHIP_CPU_MASK; + rockchip_soc_id |= (code << ROCKCHIP_CPU_SHIFT) & ROCKCHIP_CPU_MASK; +} #else #define rockchip_soc_id 0 @@ -49,13 +63,11 @@ static inline void rockchip_set_cpu_version(unsigned long ver) { } +static inline void rockchip_set_cpu(unsigned long code) +{ +} #endif -#define ROCKCHIP_CPU_MASK 0xffff0000 -#define ROCKCHIP_CPU_RK312X 0x31260000 -#define ROCKCHIP_CPU_RK3288 0x32880000 -#define ROCKCHIP_CPU_RK3308 0x33080000 - #ifdef CONFIG_CPU_RK312X static inline bool cpu_is_rk312x(void) {