Add devicetree bindings for i2s controller found on rk3399
processors from rockchip.
It's helpful to add full set of compatible strings for serials
of Rockchip SoCs (rk3066, rk3188, rk3288, rk3399).
Change-Id: Ida3f9ffecda52d81016bdb6edb640568ed8c872a
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 255edcdfab)
there maybe more than one i2s module inside chip, and these i2s modules
have different channels features.
for example: there are 3 i2s in rk3066, one support 8 channels playback
and 2 channels capture, but the others only support 2 channels playback
and 2 channels capture.
in order to compatible with these various chips, we add playback and
capture property to specify these values.
there are default channels configuration in driver: 8 channels playback
and 2 channels capture. if not add property, we use the default values.
Change-Id: I45f3214160877223ba9722bd38a36584e416b14d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit c4f9374ddc)
This patch sets the dividers autonomously.
when i2s works on master mode, and sample rates changed. We need to change
bclk and lrck at the same time for cpu internal side.
As the input source clock to the module is MCLK_I2S,
and by the divider of the module, the clock generator generates
SCLK and LRCK to transmitter and receiver.
Change-Id: I377f0f08656659787b980785fab0b69197b7b80b
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 2458c37779)
This patch like below:
----
commit 3860aa1ccf
Author: Heiko Stuebner <heiko@sntech.de>
Date: Sat Jan 9 03:18:51 2016 +0100
ARM: dts: rockchip: swap i2s clock ordering on rk3036
For sound setups using the simple-card mechanism, the main clock
(sysclk) is expected to be the first element. For the i2s-driver
itself it doesn't matter, as it uses named clocks, so we can just
swap them.
----
If we set HCLK_I2Sx at first, rockchip_i2s_set_sysclk will set the
HCLK_I2S freq (from example is 100MHz) to set the i2s_div, it is
incorrect.
Change-Id: Iab69d541c47d1293a784ebffc23f6c1ceaf9c0b1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to take care of the vop status when use rockchip_drm_crtc_mode_config,
if vop is disabled, the function would failed, that is terrible.
Save connector type and output mode on drm_display_mode->private_flags on
connector mode_fixup, then we can configure the type and mode safely
on crtc mode_set.
Change-Id: I129cf8a2f100fc19fe96f1d8985e905bea477e28
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
This patch like below:
----
commit 3860aa1ccf
Author: Heiko Stuebner <heiko@sntech.de>
Date: Sat Jan 9 03:18:51 2016 +0100
ARM: dts: rockchip: swap i2s clock ordering on rk3036
For sound setups using the simple-card mechanism, the main clock
(sysclk) is expected to be the first element. For the i2s-driver
itself it doesn't matter, as it uses named clocks, so we can just
swap them.
----
If we set HCLK_I2Sx at first, rockchip_i2s_set_sysclk will set the
HCLK_I2S freq (from example is 100MHz) to set the i2s_div, it is
incorrect.
Change-Id: I2b424ded3845b8ccd3ef233e43c5f9f915544547
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Add vpu and rkvdec resource node to enable video codec
supporting for rk3399 android.
Change-Id: I1689955858355b6061957dc43eea17f9b8d71096
Signed-off-by: alpha.lin <alpha.lin@rock-chips.com>
The Rockchip dw_hdmi driver just called platform_set_drvdata() to get
your hopes up that maybe, somehow, you'd be able to retrieve the 'struct
rockchip_hdmi' from a pointer to the 'struct device'. You can't. When
we call dw_hdmi_bind() the main driver calls dev_set_drvdata(), which
clobbers our setting.
Let's just remove the platform_set_drvdata() to avoid dashing people's
hopes.
(am from https://patchwork.kernel.org/patch/8523401/)
Change-Id: I28c4dcff37f6800b841e0492eb2613dcff7d1c81
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
This fixes a few problems in the vop crtc cleanup (handling error
paths and cleanup upon exit):
* The vop_create_crtc() error path had an unsafe version of the
iterator used for iterating over all planes (though it was
destroying planes in the iterator so should have used the safe
version)
* vop_destroy_crtc() - wasn't calling vop_plane_destroy(), which made
slub_debug unhappy, at least if we ended up running this due to a
deferred probe.
* In vop_create_crtc() if we were missing the "port" device tree node
we would fail but not return an error (found by code inspection).
Fix these problems.
(am from https://patchwork.kernel.org/patch/8523361/)
Change-Id: I3c00faca6e2fc10edc5b4576012ac28b6809a2f3
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
The drm_encoder_cleanup() was missing both from the error path of
dw_hdmi_rockchip_bind(). This caused a crash when slub_debug was
enabled and we ended up deferring probe of HDMI at boot.
This call isn't needed from unbind() because if dw_hdmi_bind() returns
no error then it takes over the job of freeing the encoder (in
dw_hdmi_unbind).
(am from https://patchwork.kernel.org/patch/8523331/)
Change-Id: Ibf5c39a5db304177a9f16d8dc691221512002348
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
When closing the DRM device while a vblank is pending, we access
file_priv after it has been free'd, which gives:
Unable to handle kernel NULL pointer dereference at virtual address 00000000
...
PC is at __list_add+0x5c/0xe8
LR is at send_vblank_event+0x54/0x1f0
...
[<c02952e8>] (__list_add) from [<c031a7b4>] (send_vblank_event+0x54/0x1f0)
[<c031a760>] (send_vblank_event) from [<c031a9c0>] (drm_send_vblank_event+0x70/0x78)
[<c031a950>] (drm_send_vblank_event) from [<c031a9f8>] (drm_crtc_send_vblank_event+0x30/0x34)
[<c031a9c8>] (drm_crtc_send_vblank_event) from [<c0339ad8>] (vop_isr+0x224/0x28c)
[<c03398b4>] (vop_isr) from [<c0081780>] (handle_irq_event_percpu+0x12c/0x3e4)
This can be triggered somewhat reliably with:
modetest -M rockchip -v -s ...
Add a preclose hook to the driver so that we can discard any pending
vblank events when the device is closed.
(am from https://patchwork.kernel.org/patch/8568111)
Change-Id: Icce075cf22f3a9d7b2157c29a47b370160b0c8d8
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
RK3399 and RK3288 shared the same eDP IP controller, so this time we
just need to append the RK3399 compatible name to analogix_dp documentation
and driver code.
Change-Id: I3fee6893c56698ee2948b9df2f3ffb7729fe75ef
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit 45970584ea (FROMLIST: drm: bridge:
analogix/dp: add some rk3288 special registers setting).
The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.
Change-Id: I8cb806d23144697225f626aaa2af19e6379dfe51
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This reverts commit 7c1abbfe2a.
Will fixes by aosp commit "mmc: block: fix ABI regression of mmc_blk_ioctl"
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Modify the 594MHz parameter for higher VCO freq to reduce the jitter.
Change-Id: I78784210b69d6895758192c84724b982fcc9e72d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Add binding documentation for the power domains
found on Rockchip RK3399 SoCs
Change-Id: I51d70a08c86b5361ac5d51151711e07ffa3046ef
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.7-armsoc/drivers commit e6e270aecb)
This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences,
which needs to have more than one power domain enabled to be operational.
Change-Id: Ie2a79aab6e1e073157c06d44252ef327caee5261
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[restructured error handling in subdomain-addition]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.7-armsoc/drivers commit 6be05b5ec1)
On some Rockchip SoC there exist child-domains only handling their
idle state with the actual power-state handled by a (shared) parent-
domain.
So allow such types of domains. For them, we can determine their
state (on/off) by checking the inverse idle-state instead.
There exist one special case if both idle as well power handling
were set as not present, but as the domain-data is defined in the
code itself, we can expect the reasonable developer to define them
in a correct way, without adding more checks.
Change-Id: Ic82cb387565a39043d5d52e62a94910de10d4bbd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.7-armsoc/drivers commit 1fe767a56c)
Not all new socs need to handle idle states on domain state changes,
so add the possibility to make them optional.
Change-Id: I46d869e1de9e03ec0664518effbcf2642053391e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.7-armsoc/drivers commit 6aa841c809)
selecting utmi interface signals from utmi interface of usb20
host0 controller to usb2phy, when phy is resumed.
Change-Id: I487e836b89177cd8bc2dc56400f4dc277c8d2bf0
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
