This patch register gpio id notifier to support USB2PHY to get extcon
message from extcon-usb-gpio.c driver. The extcon-gpio-usb.c driver
returns the state based on the ID and Vbus pin values as shown below.
State | ID | VBUS
----------------------------------------
[1] USB | H | H
[2] none | H | L
[3] USB-HOST | L | H
[4] USB-HOST | L | L
There is no need to control usb bvalid when USB_HOST state is true.
When USB_HOST state is true, we need to configure the iddig related
registers to trigger the controller's ID interrupt and set the
controller to HOST mode. When USB_HOST state is false, we need to
restore the register configuration.
Change-Id: Ia17fa67f5a26b2e5d989ede23ee6243cdc52f05f
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
The dsp_h/dsp_sty calculation for rk3506 is the same as
rk3576 vopl. The dsp_h/dest->y1 must be halved to ensure
display correctly.
Change-Id: Ia041489bd2795325519907b8a07f69fc1b3f0680
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
rk3506 SOC has two versions, which are rk3506g and rk3506b. They both
have two otg ports and uses one USB PHY with two ports. The OTG0 port
support BC1.2 detect.
They are different in that rk3506g don't have vbus and id detect pin
and use gpio to replace it. We use the extcon-usb-gpio.c driver to
manage the interrupts. If we get the EXTCON_USB state, it means that
the vbus is high and iddig is high, we enable the bvalid_phy_con to
trigger bvalid interrupt.
Change-Id: Iac0d0a992ee2d2f9664bea36d06f6b060a5bfb99
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
The process of sending commands through mcu display interface
in rk3506 is the same as rk3576 vop lite.
Change-Id: Id2d1a072befb5f13a6073ec854dab193c318f1b4
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The version read from reg VOP_LITE_VERSION is VOP_VERSION(2, 0xc),
which is the same as RV1106. But there are many differences
between RV1106 vop and RK3506 vop, we set the version to
VOP_VERSION(2, 0xe) on the software.
Change-Id: I3f6e1e24d839aaab73b728d87cfa0738c23d540b
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Since the pdm gain ctrl is moved to new register.
Change-Id: I794cba30256b011816a0894928c9377ceb90f381
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
enable dsiphy of lane0 and lane1 for rk3506
Change-Id: I939794c765d56f49a4cc91097d7174a6a3396654
Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com>
This adds the necessary data for handling otp on the rk3506.
Change-Id: I370c60b768674dfcda3942a511a120a56d250bb6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
It is needed to enable both dclk_bypass and data_bypass
in mcu mode.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I019a2242a6566fa5cfad0d9b981f020dc755c241
Add the clock tree definition for the new RK3506 SoC.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ib5e47bd03620cb7540fa827e29425c243f633a82
Add the dt-bindings header for the rk3506, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3506.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Id92261ad2a6cd68d192f2159f0f7f5edffa60a2d
Document the device tree bindings of the rockchip rk3506 SoC
clock and reset unit.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: If8c0e19fab9687d488ffce1607b8555f3e7cda35
When setting an RTC alarm, the S35390A_CMD_STATUS2 register will be
set again, which unintentionally disables the 32KHz output, this commit
adds the necessary configuration to set the S35390A_INT2_MODE_32K,
ensuring that the 32KHz output remains enabled at all times.
as a result of this change, the previous commit
7f151d9170 is no longer necessary.
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>
Change-Id: I8607899676bd624e00032eeca1a21a0658f3b71a
For force-hpd, It should be regard as always connected, so
it don't read the register to get the connect status.
Change-Id: I7082bb1ae56a640a43a800b9a934da7700e76de5
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
This is a merge error at following commit:
commit 32062f68cc ("drm/rockchip: vop2: update dsc pd status when show logo with dsc")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I603abd28fb9e1ccdbb06fa1e25c3a64b35b8d293
Read default register value and backup to regsbak must after pd power on, so we
can get correctly value, but the pd power on action depend on regsbak, so
we add extra regsbak for power_ctrl.
Fixes: 6282856b67 ("drm/rockchip: vop2: move power up plane pd before read regsbak")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I465b0ec76d4e1233c40e79528ee42b5c5c2fb727
According to the SI report, modify pe/vs configs of new
link rate R216/R243/R324/R432, which are configured to
nearby RBR/HBR/HBR2 configs in the past.
In addition, modify the pll configs to pass SSC test.
Change-Id: Ic10ea8289f47cfc93bd2c08231b76c68a6e4b4d2
Signed-off-by: damon.ding <damon.ding@rock-chips.com>
