add parameter of lcdc type for mcu to fix HDMI display abnormal when do ddr
change freq. it must update bl30 to rk3368bl30_v2.09.bin at the same time.
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
If we don't add lvds_format on the display timing, the lvds_format
value may be -1, means 0xffffffff when do register write, that is
wrong and display not works.
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
It is required to perform a reset tmdsclk action on one of the frame composer
registers changed. Or transport video and audio sample may mistake.
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
usage: add i2s dts property "rockchip,xfer-mode"
rockchip,xfer-mode = <0>: i2s transfer mode.
rockchip,xfer-mode = <1>: pcm transfer mode.
if not define, use i2s transfer mode default.
pcm transfer mode is usually used for bt/modem voice.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
If hdmi_submit_work work in synchronous mode, the malloced delayed_work
is free by caller, not by hdmi_work_queue, to prevent delayed_work is
free before flush_delayed_work fucntion is executed.
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
If we playing 4K60Hz video, and there are more than two ui layer which
is continuously refreshing, bandwith will be not enougth under ddr 456MHz.
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
While in power-down mode, the HDMI Tx PHY can be additionally set in
a lower mode of consumption by enabling the SVSRET mode, achieved by
asserting the SVSRET_MODEZ signal low.
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
EDID data readed in uboot and kernel may be different, and hdmi
output color mode is different in uboot and kernel: uboot output
RGB when EDID is wrong and kernel output YCbCr with right EDID.
But avi infomation and controller register is not set in kernel,
so the picture is wrong. Now fix this bug.
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
enter the drectory:debugfs/edp.
command as follows:
echo 0 > psr : disable psr
echo 1 > psr : config and enable psr
echo 2 > psr : sink get in psr inactive
echo 3 > psr : sink get in psr state2
echo 4 > psr : sink get in psr state3
echo 5 > psr : open phy 4 lanes
echo 6 > psr : close phy 4 lanes
Signed-off-by: linwei <buluo.lin@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
pmu idle request before cru operation to ensure the hardware
don't be reset during runing. without this hardware maybe hang
up for bus access failure.
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
