add cpus' dynamic power coefficient and update alert temperature
Change-Id: I502e49d52268b63625e01103b50e6c18fb8da8b0
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
If xin32k use the rk808_clkout1, rk808 init is too late,
xin32k enable count and prepare count is not match with it's child clk.
Change-Id: I314776c5024fdf3373619968582497e0e2d5666f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Not every rockchip efuse depends on ROCKCHIP_SIP, so delete
dependencies in Kconfig. It is more appropriate to add
dependencies for sip_smc_secure_reg_read/write.
Change-Id: I7f551f9fe71ced847657531e3c3cf418766fa3a4
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Disable uart2 since gpio mux on uart with sdmmc, and rk3368 use
fiq debugger, the uart2 could set to be disabled.
Change-Id: I2d784ccd6cf7526afc0f3bae54914e05febf91a6
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
When doing a atomic commit affecting multiple crtc's, multiple events
are generated. The user_data member does not allow you to distinguish,
because they all have the same pointer.
I've chosen to use crtc_id, because using pipe would create ambiguity
when pipe = 0. A test for != 0 is easier to implement, and crtc_id
will never be 0.
Change-Id: Ie2daba50f711f298872f15498b8d46dedb38c0ff
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Stone <daniels@collabora.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9272895/)
Backlight polarity not works without pwm_adjust_config.
Change-Id: I11e5eefe340f758b6721021f13238306b3721270
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
On some rockchip platforms, need use secure interface to access efuse.
Change-Id: I49a4d5e547b689ff1665f1eb29a1dbbba5ef2595
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
HAVE_ARM_SMCCC is default selected by ARM(if CPU_V7) or ARM64
Change-Id: I4bc64d4c98de5fad3179b3121b0f361d6337732c
Signed-off-by: chenjh <chenjh@rock-chips.com>
NPLL is used for vop dclk, sync rate flag would cause loader display
abnormal.
Change-Id: Ia170a8d0b7d1f39e2c9dcbc10b5d33fd1886d5f7
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
NPLL is used for display pixelclock, assign clock rates would overlap
loader pll setting, cause display abnormal.
Change-Id: Iaf1094c43526c7ca7b364608fa7153d03f84326c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
The INNO MIPI D-PHY is built in witch a standard digital interface
to talk to any third part Host controller.That is part of Rockchip SoCs,
like rk3368.
Change-Id: I9806882e0e3fb6b20348015d0f34923d1bc46b89
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
when pd power on/off, the qos regs need to save and restore.
Change-Id: I34146660e75609517463d679271386b536401b20
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
As GPU share voltage domain with DDR and the minimum voltage of DDR
696MHz is 1100mV, GPU's voltage must be equal or greater than 1100mV.
After add ddr frequency scaling support, we can change them again.
Change-Id: I761931675265aac75425bf1cc9c7280a33f91e16
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
HDMI PD is power off when system suspend, so ih_mute register
bit0 mute_all_interrupt will be reset to 1 when system resume.
HPD interrupt will be mask, that would cause hdmi plugin could
not be detected.
Change-Id: I3bf2e6116e902cd516a7ac69fbe8569ca943e853
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Before this patch, clust1 has little core0~3, clust0 has big core0~3
cpu_l | cpu0 |
cpu_l | cpu1 | clust1
cpu_l | cpu2 |
cpu_l | cpu3 |
----------------------
cpu_b | cpu4 |
cpu_b | cpu5 | clust0
cpu_b | cpu6 |
cpu_b | cpu7 |
With this patch, clust0 will have little core0~3, clust1 will have big core0~3
cpu_l | cpu0 |
cpu_l | cpu1 | clust0
cpu_l | cpu2 |
cpu_l | cpu3 |
----------------------
cpu_b | cpu4 |
cpu_b | cpu5 | clust1
cpu_b | cpu6 |
cpu_b | cpu7 |
It makes no other change, just keep same with other SoCs definations.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9625109/)
Change-Id: I1beea4d3e75409d3a1f1614b0b86f1a929db4eee
We need this to ask PCIe bus allocater to always
assign 0 to our root bus isntead of increasing it
, otherwise the hierarchy would be wrong if we unbind
and bind the root port.
Change-Id: I4ada61c89e617c7bccd92c5f9fa3334cae40603e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Add pci_unmap_iospace() to undo what pci_remap_iospace() did.
This is needed to support hotplug removal of host bridges that use
pci_remap_iospace().
Change-Id: Iee5d778cb8ddfedab59c55c227a8c60825786854
[bhelgaas: changelog]
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
(cherry picked from 4d3f138459)
Conflicts:
drivers/pci/pci.c
rockchip_pcie_probe() calls of_pci_get_host_bridge_resources() to parse
resources from DT and build a resource list. The caller is responsible for
disposing of the resource list. This is normally done by
pci_release_host_bridge_dev() when the host bridge is removed.
If the host bridge probe fails, dispose of the resource list in the probe
error path.
Change-Id: Iefc17963a6ce99c64f2940d8dc2ba93bd00fe120
[bhelgaas: changelog]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from f1d722b607)
