This change adds usb otg/host controllers and related phy nodes
on rk3308 SoC.
Change-Id: I5fd3acc44614cc3fcb58eb269c2e559ea24ab0f1
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This change adds usb-phy support for rk3308 SoC and amend related
phy Documentation.
Change-Id: I953af94fb4d55d79ae1cba624a04fb4b84e019f6
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The commit dc71e51944 ("usb: dwc2: make otg manage lowlevel
hw on its own") aimed to control the clk and phy power for
otg mode, but it also introduced lost of new problems, so we
revert it.
This patch only controls phy power for otg mode, it can fix
the dwc2 udc start fail issue with the following error log:
dwc2_hsotg_init_fifo: timeout flushing fifos (GRSTCTL=80000430)
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
bound driver configfs-gadget
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
Change-Id: Id6996aecab7f0aaaf12530b7a377144e23ef1667
Signed-off-by: William Wu <william.wu@rock-chips.com>
This reverts commit dc71e51944.
We found that this commit will cause at least three issue:
1. On RK3126C Tablet, plug in OTG cable and U disk first,
then power on the Tablet, the system will hang because
of dwc2 interrupt storm.
2. On RK3328-EVB, connect usb to PC first, then power on
the board, the system will hang because of dwc2 interrup
store.
3. On Linux system, the OTG Host mode can't detect U disk.
The root cause is that this patch will diable the controller
clk at the end of probe if OTG work as OTG mode, and only
enable the clk again in dwc2_hsotg_udc_start(). However,
the dwc2 interrupt is enabled in dwc2_hcd_init() during probe,
so the dwc2 interrupt maybe triggered but the interrupt pending
state can't be cleared because that the clk has been disabled.
This cause dwc2 interrupt storm problem.
On the other hand, for Linux system, it may config OTG work
as OTG mode, but it never calls dwc2_hsotg_udc_start() to
enable the controller clk becasue there is no gadget application.
So the clk never be enabled, and casue OTG Host mode fail
to detect the U disk.
Change-Id: Id3463225e0232de7078de1e9d39470a6d5e2cea4
Signed-off-by: William Wu <william.wu@rock-chips.com>
add devfreq and devfreq_cooling feature for gpio-fan and then
it can be used as thermal cooling device to support IPA thermal
policy.
Change-Id: I376faa485625ac41276df9bbac8188ea8d664b36
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
add support for rgb panel or rgb covert to other interface panel.
Change-Id: I190ce6e08d38f794ecabb863e0def5e74890f75a
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
There are two clocks between armclk and pll_apll on px30,
but there may be only one clock on some Socs, so it will
get a error pll clock.
Change-Id: I34116a1ec824b884d3745082f3546cd9ab4c0d21
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add constants and callback functions for the dwmac on rk3308 soc.
The base structure is the same, but registers and the bits in
them moved slightly, and add the clk_mac_speed for the select
of mac speed.
Change-Id: Ieaea3ade9e51d5118f0eb855d8e02febfb2275d1
Signed-off-by: David Wu <david.wu@rock-chips.com>
The MMC sample and drv clock for rockchip platforms are derived from
the bus clock output to the MMC/SDIO card. So it should never happens
that the clk rate is zero given it should inherits the clock rate from
its parent. If something goes wrong and makes the clock rate to be zero,
the calculation would be wrong but may still make the mmc tuning process
work luckily. However it makes people harder to debug when the following
data transfer is unstable.
Change-Id: Ifeb4c063cb73e0a444fd8819ef3128256331cd7a
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from https://patchwork.kernel.org/patch/10258071/)
If the mac_refclk is provided from mac controller, the pin of mac_refclk
needs to setup 12ma strength, or the signal is not good.
If the mac_refclk is provided from phy, the pin of mac_refclk needs not
to setup 12ma strength, the phy would do it.
Change-Id: I4f6e6d081b4616363d10358c9e36d71cacbdb134
Signed-off-by: David Wu <david.wu@rock-chips.com>
Opp rate is used to calc power in thermal framework, so we record
this rate instead of real clock rate.
Devfreq is not ready in target() when use performance governor, so
we need record opp rate in probe().
Change-Id: Iec1918ad5d12124b9f112964f247339e0d50645f
Signed-off-by: Liang Chen <cl@rock-chips.com>
400MHz and 600MHz aren't supported at present.
This had submitted in commit a8c497e79d
("arm64: dts: rockchip: rk3328: Disable 400MHz and 600MHz for dmc")
but was modified in commit 59af91b563
("arm64: dts: rockchip: auto select opp-table by leakage for rk3328")
by mistake.
Change-Id: I864453d16596798e063a2c3569b260fd1a95c209
Signed-off-by: Liang Chen <cl@rock-chips.com>
In the bandwidth tension environment when close win2, vop will access
the freed memory lead to iommu pagefault. so we add this reset to workaround.
Change-Id: I22b0c0f145d042e3aaf98fb45ffff6304c93963c
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Because when enable uboot logo display, vop_crtc_enable() will not be
called when power on, this will lead to some vop initial like
axi channel and some debug irq will not be enabled. so we move some
config to vop_initial() and call from vop_crtc_loader_protect().
Change-Id: I86f02e2e7d12b78cce17e278baaf6dff93137167
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
some version vop unsupport pixel alpha add scale, this case
will lead to display error and post empty.
Change-Id: I32820a14292b46ce61fd30bfccdaa5e4f635de49
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The most pins of rk3308 are 2bits iomux, but the banks's register
width is 0x8.
Change-Id: I3305810b3f75febd6ec7a933b65e3c9d50f003dd
Signed-off-by: David Wu <david.wu@rock-chips.com>
This adds the necessary data for handling io voltage domains on the rk3308.
As interesting tidbit, the rk3308 contains one iodomain area at grf,
Change-Id: Ife72a284a8926d02ef5df7a422d41924494d0300
Signed-off-by: David Wu <david.wu@rock-chips.com>
