gpio0_D is unavailable on rk3288 with current pinctrl driver.
Change-Id: I7d38ebd3b00ac0df31861406f758bdd9e57f9903
Signed-off-by: xcq <shawn.xu@rock-chips.com>
This reverts commit 1d9964a989.
Double confirmation, GPIO0_D0 ~ GPIO0_D7 pins are not connected to pad,
this is a wrong commit, revert this commit.
Change-Id: Iebec11ee47a68fe51ec90361fd412d05df832998
Signed-off-by: David Wu <david.wu@rock-chips.com>
First, write hdcp key by "ProvisioningTool" if you want to
enable hdcp function, or else will auth fail.
To check whether the hdcp is enable or not
#cat /sys/class/misc/hdmi_hdcp1x/enable
0:hdcp is disabled
1:hdcp is enabled, hdmi screen will be pink if it is failed;
2:hdcp is enabled, hdmi screen will be normal if it is failed;
Enable or disable hdcp function
#echo 0 > /sys/class/misc/hdmi_hdcp1x/enable
#echo 1 > /sys/class/misc/hdmi_hdcp1x/enable
#echo 2 > /sys/class/misc/hdmi_hdcp1x/enable
Get the status of hdcp
#cat /sys/class/misc/hdmi_hdcp1x/status
The result will be one of the follow list:
hdcp disable;
hdcp_auth_start
hdcp_auth_success;
hdcp_auth_fail;
unknown status.
Change-Id: Iac6c7d6a1196ce9cf2869d7916bbe6c8941ec13b
Signed-off-by: xuhuicong <xhc@rock-chips.com>
This patch exports sdio src clock for dts reference.
Change-Id: I3e83cce4da3d82af4b18df43ecd51c504d308c02
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
According to spec, TMDS driver should power up between PLL
power up and PLL lock.
There is an mistake of pdata en register, the real register
is reg2 bit0, not reg1 bit0.
Change-Id: I9d2b707cbcfd70b63f4a1a277a85f21b62643d2e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Actually vop hardware has no output height limit, so no
need limit display with max_output.height
Change-Id: Ide70cb28af9a23c1a12c068168b13aac37041b28
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
In order to get lower jitter clock for hdmi tmds, Hardware
design that: direct get tmds clock from vpll, bypass vop.
This design can make hdmi good works, but also limit hdmi's
clock source, the vop which hdmi use need also assign to vpll,
and use same clock rate, it's hardware limitation.
This patch add a mechanism to select dclk's parent pll, then
can allocate correct pll for hdmi.
Change-Id: I9e3b4b6d3756c409782df0605706be4203d69a32
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Suggested-by: Heiko Stuebner <heiko@sntech.de>
dmaengine_prep_dma_cyclic, to use buf_addr with size buf_len,
generate an interrupt every period_len. But DMA must restart
every period_len, it may be blocked. If i2s use it, it may
cause sound break. Infiniteloop is helpful to solve this
issue. In infiniteloop mode, when DMA transfers all buf_len
data, it goes back to the start of buf_addr and continue to
transfer endless.
Change-Id: Ibbc92c416d0a9dd58633e7991176c86300c3da98
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Because we have supported to force otg mode for rk3328 in the commit
2b9b897141f1 ("phy: rockchip-inno-usb2: support to force otg mode"),
so let's config dr_mode as otg for usb otg port, and then user can
use otg peripheral mode and host mode as needed.
Change-Id: I6f55fb2aad1b8c49498af829475a8b59215251e5
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adds otg vbus gpio for usb2 phy0, and then we
can control otg vbus for otg host mode.
Change-Id: I685060270f9cb0963931a84035cad7286d99a469
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch creates an usb2 phy attribute group and
provides an attribute "otg_mode" for otg port to
force otg mode independently of the voltage of otg
id pin.
In order to implement the force mode function, we can
select otg plug indicator output (AKA iddig) from GRF,
and set GRF USB otg plug indicator to "0" or "1" to
control iddig status.
We only support rk322x/rk3328 to force otg mode for
the time being.
And we need to disable usb auto suspend function if
we want to force otg mode. Add 'usbcore.autosuspend=-1'
in cmdline to disable usb auto suspend.
Usage:
[1] Force host mode
echo host > /sys/devices/platform/<u2phy dev name>/mode
[2] Force peripheral mode
echo peripheral > /sys/devices/platform/<u2phy dev name>/mode
[3] Force otg mode
echo otg > /sys/devices/platform/<u2phy dev name>/mode
Legacy Usage:
[1] Force host mode
echo 1 > /sys/devices/platform/<u2phy dev name>/mode
[2] Force peripheral mode
echo 2 > /sys/devices/platform/<u2phy dev name>/mode
[3] Force otg mode
echo 0 > /sys/devices/platform/<u2phy dev name>/mode
Change-Id: I875b60b0390e3bd9af34b740cba8f5d53e1df752
Signed-off-by: William Wu <william.wu@rock-chips.com>
this driver only support h264e & h265e. if you want to
enable the driver, you must modify the menuconfig and
turn on MPP_SERVICE & MPP_DEVICE.
Change-Id: I7f1c6e473eaf7aedb4fa86791412b5fbcb2c531d
Signed-off-by: buluess.li <buluess.li@rock-chips.com>
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>
we found mclk maybe not precise as required because of PLL,
but it still can be used and no side effect. for example, if we
require mclk 11289600, but get 11289598, it doesn't matter.
so using DIV_ROUND_CLOSEST to fix it.
Change-Id: If8453a7a08b319da81b07d572b02247bd7e7bd27
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit would enable the VDPU and RKVDEC devices.
The VDPU works in the non combo mode.
Change-Id: I643350d5a2ac17759984fda2e95fb2b82701e7cf
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Even the same type video IP would request a different numbers
of reset control.
From the RK3328 times, the video IP also request decrease the
frequency of the clock to lower than 300 MHZ before resetting.
It seems no hard to apply it into the previous platform.
Change-Id: Iacf1accf24c8776bb8b425b613e6e34215380203
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Jung and I meet some problem the video decoder, so
we just release the VDPU standalone this time.
It seems that the iommu can't attach to two different
IP at the same time.
Change-Id: I24d73cd5ab2c3d32da6ef29661061c7fda9186f2
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Add "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc" for
dwmmc on rk322x platform.
Change-Id: I8217d237260a33ce5b115080cf4d41ad4a5733e8
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
