For those sub modules that have shadow registers in core isp, the
new programing parameters would not be active if both
CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT and CFG_UPD are not set. Now
we configure CFG_UPD to force update the shadow registers when new
ISP parameters are configured.
BUG=b:36227021
TEST=scarlet can preview, LSC data table can be switched.
Change-Id: I804ddfc45b3c2fca9a6f51627af4264a25075070
Signed-off-by: ZhongYiChong <zyc@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/942721
Commit-Ready: Tomasz Figa <tfiga@chromium.org>
Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Rather than adding unnecessary indirection, just use stream index to
handle MI interrupt enable/disable/clear, since the stream index matches
the order of bits now, thanks to previous patch. While at it, remove
some dead code.
BUG=b:78779539
TEST=Make sure camera works on scarlet.
Change-Id: Ie817471972e60917250d7240d7543b516db0db03
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1065404
Reviewed-by: yichong zhong <zyc@rock-chips.com>
Reviewed-by: Alexandre Courbot <acourbot@chromium.org>
The current order (SP=0, MP=1) is the opposite of what is there in
hardware registers (MP=0, SP=1), which unnecessarily complicates the
code that deals with hardware programming. Fix this by reversing the
order of streams in the driver.
BUG=b:78779539
TEST=Make sure camera works on scarlet.
Change-Id: I43671748073d9dc4cb906e5f6f992f870920ce91
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1065403
Tested-by: yichong zhong <zyc@rock-chips.com>
Reviewed-by: Ricky Liang <jcliang@chromium.org>
Reviewed-by: yichong zhong <zyc@rock-chips.com>
Reviewed-by: Alexandre Courbot <acourbot@chromium.org>
The rkisp1_state enum consists only of 3 entries, where 1 is completely
unused and the other two respectively mean not streaming or streaming.
Replace it with a boolean called "streaming".
While at it, remove "saved_state" member from rkisp1_stream struct, as
it is not used anywhere.
BUG=b:78779539
TEST=Make sure camera works on scarlet.
Change-Id: I329b62951e214a25ac35a5c189814cebba26dbf1
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1059006
Tested-by: yichong zhong <zyc@rock-chips.com>
Reviewed-by: Ricky Liang <jcliang@chromium.org>
Reviewed-by: yichong zhong <zyc@rock-chips.com>
Reviewed-by: Alexandre Courbot <acourbot@chromium.org>
This patch adds superspeed descriptors in device
applications to support USB 3.0 ffs gadget.
Change-Id: I5a364c935b1d30e2e929791ff16a34cf0d1c87e1
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to P45 of <<Rockchip RK3308 Datasheet V1.0-20180313>>,
the max voltage for Logic is 1.1V, so for many boards which
Core_VDD and Logic_VDD share the same power supply, the ARM
core voltage will be limited to 1.1V, that can only guarantee
the cpu to run at the max freq of 1008MHZ.
As for board which Core_VDD and Logic_VDD use independent
power supply, the cpu can run a higher freq up to 1296MHZ
with higher Core_VDD power supply, you can eanble it in
your board dts.
Change-Id: I69777aa5bee797e609d9ea122f3502347930b631
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The userspace might check tty information in proc fs.
Change-Id: If3e81aacbc7948dd3000606702296bc2b76bec09
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Some boards don't need to control power supply.
Let's make it optional.
Change-Id: Ifd72a7c3704cdc0df4f2d2096278a6b58f925e8d
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
The msleep < 20ms can sleep for up to 20ms, see:
Documentation/timers/timers-howto.txt.
Change msleep to usleep_range for this case.
Change-Id: Ibb680b766b6c7317fc1f13dfda7457ef771b4272
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
According to the hardware design, wifi and rmii cannot be powered off in
deepsleep
Change-Id: Id44ef9b31c34b6f12695dbf3fbb843950602ca71
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
This patch fix snd_pcm_vad_attached crash when using non-soc audio,
such as usb audio, pci audio. it is because substream private_data
in these types of audio framework means different values.
Change-Id: I5dcd3ea7de363bc3afc8d9879a2a37c6d6110a4a
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
We need to operate loopback ADCs during LINEOUT enable
or disable that it make ensure enable ADCs more smoothly.
Therefore, we don't need to reset loopback ADCs in
rk3308_codec_loopback_work(), and separete reinit-mics
from adc_ana_enable().
Change-Id: Id26dd5ad00c527be47a706df58c435f12d46c281
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch using BIST mode switching to fix the glitches
during loopback and reset ADCs.
Change-Id: Icb9dbd6557736fe555d9f8296369571e78bc6844
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Compress kernel use LZ4 for faster boot time.
zImage larger 15~20%, but save about 75% time. For example:
size(byte) time(s)
zImage (gz) 2891776 0.177
zImage (lz4) 3334144 0.042
Change-Id: I6a65569bbfc41eb63ee4154df26d055af7aa4ce7
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This adds a adv7181 driver that can receive cvbs in and
output NTSC yuv data.
Change-Id: I1f86178b38fd079f790f1194304e5b94f72e523f
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Because px3se evb board enables fiq-debugger on uart1,
this disables uart1 and set uart1 iomux in fiq-debugger.
Change-Id: I0432216ee2162699309605c72600ad56a1e6c7b9
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Add firefly linux ov13850 camera node, and enable isp
and isp_mmu.
Change-Id: I317f4b9895c73913456c957273cc6b18173a8cd9
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
1.Read ECC status according to each flash's identify Internal ECC;
2.Refresh data before reach ECC Flipping Bits.
Change-Id: Ie33850e151410cd788ff0220041d041a3d5b4f07
Signed-off-by: Dingqiang Lin <jon.lin@rock-chips.com>
