We use phy_set_bus_width() to set the lane rate that the PHY supports.
The controller driver may then use phy_get_bus_width() to fetch the
PHY lane rate in order to properly configure the controller.
Change-Id: I116f0d82ad187806914c0d566eab92b922f143ef
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
1) If using the third part PHY, we use phy_get_bus_width() to fetch the
PHY lane rate in order to properly configure the controller.
2) Removed unneeded code.
Change-Id: I5c245e65f58665aa5fc025d6579e8bb331554458
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
In future it will be modified to support more rockchip platforms.
Change-Id: I5cd7ce555eefe08b12fbfcda8ef445c4b169e8c6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
In order to get correct results from sysfs, e.g.:
cat /sys/class/devfreq/dmc/min_freq
cat /sys/class/devfreq/dmc/max_freq
Change-Id: Id5921fdbacd0977c0b5378ccf0de068f0195b557
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Set system_serial_low/high from eFuse ID.
Serial can read from /proc/cpuinfo.
Change-Id: If412fc5a89a5e5092b510452fc5a126fdd374ac2
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Use a new compatible to match secure interface
when kernel is in no-secure mode.
Change-Id: I3994b2c86bb9e221f102766c2d1a341930628b5d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This adds the necessary data for handling secure efuse on the rk3288.
Need to use secure interface to access efuse when kernel is in no-secure
mode.
Change-Id: I1979f23ed8f85c9eb248de276b32adcbb165bd79
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Cat ddr frequency from rockchip_ddrclk_scpi_set_rate prior to
rockchip_ddrclk_scpi_recalc_rate, to optimizing running time and reduce
SCPI APIs usage rate.
Change-Id: Iba31d33a5920816b1cc230f639ea3a9503d451c8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
1. amend return frequency for scpi_ddr_set_clk_rate.
2. add scpi_ddr_dclk_mode function for rk3368.
Change-Id: I0f3c42d74e34ccb740f2a9e68ef12bba98b7aab7
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
The function doesn't get something from dts, it is more appropriate to
rename of_get_opp_table to rk3399_dmcfreq_init_freq_table.
Change-Id: I8c4994d45ff4d0654d034483e091bbb225a1ea61
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This adds the necessary data for handling dfi on the rk3368.
Access the dfi via registers provided by GRF (general register
files) module.
Change-Id: I96c2b4dcd34d90731b749ebdbe6922f01559d8e6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3368 platform in future.
Change-Id: Ie7fd2e8d8bdf8b9ff843ca13e848f772adaa109a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
On rk3368, let a mcu scaling ddr clock via SCPI (System Control and
Power Interface) APIs.
Change-Id: I95342b876caad991e6d1319c5e4ec793365c7981
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
update some features:
1. rename sip smc function name;
2. add serial hw irq and phyical base address parse;
3. use FIQ_DEBUGGER_TRUST_ZONE for armv7 and armv8.
Change-Id: I920899f30cadf1ec8380a2e70f5d1e0e801ec5c2
Signed-off-by: chenjh <chenjh@rock-chips.com>
This adds fixed below errors when compiled rockchip_defconfig without
CONFIG_RK3368_SCPI_PROTOCOL select:
In file included from drivers/clk/rockchip/clk-ddr.c:23:0:
include/soc/rockchip/scpi.h:89:12: warning:
'scpi_sys_set_jtagmux_on_off' defined but not used [-Wunused-function]
error, forbidden warning: scpi.h:89
scripts/Makefile.build:258: recipe for target
'drivers/clk/rockchip/clk-ddr.o' failed
make[3]: *** [drivers/clk/rockchip/clk-ddr.o] Error 1
Change-Id: I5abc184554dcfc3697be82aede8dec27da2fcdd9
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
GPU and DDR share vdd_logic.
DDR DVFS is not ready yet, to ensure DDR could work stably,
vdd_logic(vdd_gpu) should be higher than 1.05V.
This would be optimized after DDR DVFS is ready.
Change-Id: I2749484c7f6f86dde850f0f85d606e1c1ab85c17
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
