Add the bandgap entry for OMAP4430 devices.
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
[benoit.cousson@linaro.org: Add blank line and fix reg presentation]
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
On most OMAP3 platforms, the twl4030 IRQ line is connected to the
SYS_NIRQ line on OMAP. Add another DTS include file
(twl4030_omap3.dtsi) for boards that hook up the twl4030 this way
to include.
This allows RTC wake from off-mode to work again on OMAP3-based
platforms with twl4030. Tested on 3530/Beagle, 3730/Beagle-xM,
3530/Overo, 3730/Overo-STORM.
Special thanks to Florian Vaussard for suggesting use of preprocessor
feature.
Cc: Florian Vaussard <florian.vaussard@epfl.ch>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Using the gpio-keys bindings, configure the user button on Beagle
boards. Since the user button is enabled as a wakeup source, also
ensure the GPIO pin is mux'd correctly and has IO ring wakeups enabled,
so it can also wakeup from off mode.
Special thanks to Florian Vaussard for suggesting the preprocessor
feature.
Cc: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Ensure the console uart (UART3) on these boards is mux'd correctly, and
IO ring wakeup is enabled.
This is needed for serial console wakeups when using DT boot.
Thanks to Florian Vaussard for suggestion to use preprocessor
features.
Cc: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting omap5 uevm results in the following error
"did not get pins for uart error: -19"
This happens because omap5 uevm dts file is not adapted
to use uart through pinctrl framework.
Populate uart pinctrl data to get rid of the error.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
[r.sricharan@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add support for blue LED 1 off of GPIO 153.
Make the LED a heartbeat LED
Configure the MUX for GPIO output.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
[r.sricharan@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Provide the RESET regulators for the USB PHYs, the USB Host
port modes and the PHY devices.
Also provide pin multiplexer information for the USB host
pins.
Signed-off-by: Roger Quadros <rogerq@ti.com>
[r.sricharan@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The uevm is the only official board supported for the OMAP5 soc
in mainline. The existent sevm platform will no more be supported.
Hence cleaning up the board dts file to have only the data
required for uevm.
Renaming the board dts file and adding the following cleanups.
* There are no devices connected on I2C 2,3,4 buses. So remove
the pinmux data for the same.
* OMAP5432 and DDR3 memory is used in the uevm. Temperature polling
is not supported with DDR3 memories. Because of DDR3 phy limitation
the voltage change across DVFS and all shadow registers for DVFS on
DDR3 is not supported. Hence the emif kernel driver is not required,
so removing the DDR3 device file and emif nodes for uevm.
* Keypad is not supported on uevm. So remove the device node.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Using constants for pinctrl allows a better readability, and removes
redundancy with comments.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Tested-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The pinctrl IP inside the AM33XX family differs slightly from
what is found on OMAP2+. Define a specific header to take account
of the differences.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Tested-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Replace /include/ by #include for AM33XX and AM35XX device tree
files, in order to use the C pre-processor, making use of #define
features possible.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Tested-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
DT source (minimal) for AM4372 SoC to represent AM43x SoC's. Those
represented here are the minimal DT nodes necessary to get kernel
booting.
In DT nodes, "ti,hwmod" property has not been added, this would be
added along with PRCM support for AM43x.
Signed-off-by: Ankur Kishore <a-kishore@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Update the dt property ti,audpwron-gpio to use the
gpio macro definition for GPIO_ACTIVE_HIGH.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.
A1-A3 = gpio_wk7
ES = gpio_110
There is no change to LED D2
Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
GPMC controller on AM335x-EVM has a NAND flash connected to it.
This patch updates following in am335x-evm.dts:
- adds nandflash specific pin-mux configs
- adds nand node as child of GPMC contoller, with information about
NAND flash interface, NAND partition table, ECC scheme, elm handle id.
- updates GPMC node for newer GPMC DT properties added in linux-3.10.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Signed-off-by: Gupta, Pekon <pekon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
ELM hardware engine is used for locating bit-flips in NAND data
This patch is required for working of hardware based NAND ECC schemes
with DT support.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The IGEP COM Module has an 512MB NAND flash memory.
Add a device node for this NAND and its partition layout.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The IGEPv2 board has an 512MB NAND flash memory.
Add a device node for this NAND and its partition layout.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The IGEPv2 board has an SMSC LAN9221i ethernet chip connected to
the OMAP3 processor though the General-Purpose Memory Controller.
This patch adds a device node for the ethernet chip as a GPMC child
and all its dependencies (regulators, GPIO and pin muxs).
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
xdma_event_intr1.clkout2 pad can be used to source clock
from either 32K OSC or any of the PLL (except MPU) outputs.
On the existing AM335x based boards (EVM, EVM-SK and Bone),
this pad is used to feed the clock to audio codes.
So, this patch configures the pinmux to get clkout2 on the pad.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add pin control binding for UART0 device nodes in all
board specific DT files.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Matt Porter <mporter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
With DT support, where naming convention is based on base-addr
and not id, so we should follow TRM/Spec numbering label.
This patch changes UART numbering as per TRM, as uart0-5.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Matt Porter <mporter@ti.com>
Cc: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Now gpio-leds driver is using devm_pinctrl_get_select_default()
api to set default pinmux configuration required for the
functionality of the driver, so this patch moves respective
pinctrl binding inside leds node.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add pin control binding for I2C device nodes in all
board specific DT files (as per current usage),
EVM: Both i2c0 and i2c1
EVM-SK and Bone: Only i2c0
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Matt Porter <mporter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The carveouts that have been reserved for multimedia usecases
are not being used currently by any driver and so have been
cleaned up. Memory will be allocated runtime through CMA for
enabling the multimedia usecases.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The SDIO device in Lynxpoint has its LTR registers reserved for a
WiFi device (a child of the SDIO device) in the ACPI namespace even
though those registers physically belong to the SDIO device itself.
In order to be able to access the SDIO LTR registers from the ACPI
LPSS driver for diagnostic purposes we need to use a size override
for the SDIO private register space.
Add a possibility to override the size of the private register space
of an LPSS device provided by the ACPI tables in the ACPI LPSS driver
and set the correct size for the SDIO device in there.
[rjw: Changelog]
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Intel LPSS provides an extra TX byte counter and an extra TX
completion interrupt for some of its bus controllers. However,
there is no use for the extra UART interrupt and it has to be
masked out during initialization.
Otherwise, if the firmware does not mask the interrupt and
the driver does not clear it, it may cause an interrupt flood
freezing the board to happen.
Add code masking that problematic interrupt to the ACPI LPSS driver.
[rjw: Changelog]
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Intel BayTrail has almost the same Low Power Subsystem than Lynxpoint with
few differences. Peripherals are clocked with different speeds (typically
lower) and the clock is not always gated. To support this we add
possibility to share a common fixed rate clock and make clock gating
optional.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
CONFIG_ACPI_HOTPLUG_MEMORY has been changed to bool (y/n), and
its module option is no longer valid. So, stop using
CONFIG_ACPI_HOTPLUG_MEMORY_MODULE.
Signed-off-by: Toshi Kani <toshi.kani@hp.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This reverts commit 55a68c23e0.
In order to avoid a collision with dw_apb_timer changes in
the arm-soc tree, revert this change.
I'm leaving it to the arm-soc folks to sort out if they want
to keep the other side of the collision or if they're just going
to back it all out and try again during the next release cycle.
Reported-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
If device is initialized from device tree, but has no interrupt
assigned, uio will still try to request and interrupt old way,
fails, and fails registration.
This is wrong; don't try initializing irq using platform data if
device tree is available.
Simplified code based on suggestion by Grant Likely.
Fixed memory leak in "irq can not be registered" error path.
Signed-off-by: Pavel Machek <pavel@denx.de>
Reported-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This adds ability to bind uio driver to given open firmware device
using command line option. Thus, userspace driver can be developed and
used without modifying the kernel.
Signed-off-by: Pavel Machek <pavel@denx.de>
Tested-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This driver exports the memory area associated with the mezzanine card
as a misc device, so users can access registers.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch>
Acked-by: Emilio G. Cota <cota@braap.org>
Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This driver allows to reprogram the EEPROM in a mezzanine, to store
its own identifiers during manufacturing or to save other useful data.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch>
Acked-by: Emilio G. Cota <cota@braap.org>
Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This simple do-nothing mezzanine driver shows how to write a mezzanine
driver, that can also handle interrupts reported by the carrier.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch>
Acked-by: Emilio G. Cota <cota@braap.org>
Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This fake carrier is designed to help FMC users understand how a
carrier driver works, and to experiment the behaviour with EEPROM
reprogramming (with a mezzanine driver commited later). This carrier
can register up to 4 (fake) mezzanines.
We have real carriers (both on PCI-E and VME), but they are bigger
things and are not part of this submission.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch>
Acked-by: Emilio G. Cota <cota@braap.org>
Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This is selected sections of the current manual for fmc-bus, as
developed outside of the kernel before submission.
Like the other patches in this set, it corresponds to commit ab23167f of
the repository at ohwr.org
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch>
Acked-by: Emilio G. Cota <cota@braap.org>
Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Acked-by: Rob Landley <rob@landley.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This module offers registration services for both carriers
(i.e. devices) and mezzanines (i.e. drivers). The matching for devices
and drivers is performed according to the IPMI standard for FRU
devices (Field Replaceable Units).
The code includes support for parsing an SDB tree if present in the FPGA,
and dumping it for diagnostics. SDB is not mandatory.
Files in this commit correspond to commit ab23167f in the master branch
of the project hosted on ohwr.org.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch>
Acked-by: Emilio G. Cota <cota@braap.org>
Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This hopefully will help point developers to the proper way that patches
should be submitted for inclusion in the stable kernel releases.
Reported-by: David Howells <dhowells@redhat.com>
Acked-by: David Howells <dhowells@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Currently, randconfig may set more than one symbol in a given choice.
Given this config file:
config A
bool "A"
if A
choice
bool "B/C/D"
config B
bool "B"
config C
bool "C"
config D
bool "D"
endchoice
endif # A
Then randconfig generates such .config files (case where A is not set is not
shown below for brevity), and where only the right-most .config is valid:
CONFIG_A=y CONFIG_A=y CONFIG_A=y
CONFIG_B=y CONFIG_B=y CONFIG_B=y
CONFIG_C=y # CONFIG_C is not set # CONFIG_C is not set
# CONFIG_D is not set CONFIG_D=y # CONFIG_D is not set
That is, in a randomised choice, the first symbol is always selected,
and at most one other symbol may be selected.
This is due to symbol randomised in a choice not being properly flagged
as having a value.
Fix that by flagging those symbols adequately: have a user-defined value,
and be not valid (to force recalculation of the symbol).
Note: if the choice is not conditional, then the randomisation is properly
done.
Reported-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
[yann.morin.1998@free.fr: independently re-done the same patch as Matthieu,
as pointed out by Sedat]
Cc: Arnaud Lacombe <lacombar@gmail.com>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
