On TC2, all CPUs in a cluster are woken up when an IRQ event triggers for a
CPU in a cluster in shutdown state.
This patch puts spuriously woken CPUs back in reset by checking the
pending IRQ status in the SPC wake-up interrupt status register; if the
CPU has no pending IRQ routed to it, the core reexecutes wfi and it is put
in reset by FW straight away.
Tested-by: Viresh Kumar <viresh.kumar2@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Change the init code for cpuidle-tc2 to check for a
compatible node in the devicetree of "arm,generic"
in preparation for moving it to driver/cpuidle.
Rename functions / variable from tc2_ to bl_.
Signed-off-by: mark hambleton <mahamble@broadcom.com>
Use the bL_cpu_suspend method instead of bL_cpu_power_down.
This allows for the driver to become usable on non SPC based platform
such as RTSM if vexpress_spc_check_loaded() is removed.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
The functions in mcpm_entry.c are mostly intended for use during
scary cache and coherency disabling sequences, or do other things
which confuse trace ... like powering a CPU down and not
returning. Similarly for the backend code.
For simplicity, this patch just makes whole files notrace.
There should be more than enough traceable points on the paths to
these functions, but we can be more fine-grained later if there is
a need for it.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
This is simplistic for the moment as the expected residency is used to
prevent the shutting down of L2 and the cluster if the residency for
the last man is lower than 5 ms. To make this right, the residency
end time for each CPU would need to be recorded and taken into account.
On a suspend, the firmware mailbox address has to be set prior entering
low power mode.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
On TC2 testchip the GIC CPU IF must be disabled before powering down a
core since a pending IRQ might cause wfi completion and the processor
would exit wfi state while power controller is taking action to reset or
power up the CPU upon IRQ reception.
This patch adds code that disables the GIC CPU IF in TC2 specific
power API methods.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This should be queued right before 'Revert "ARM: common: add GIC bybass disable
on GIC CPU IF save function"'.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
To deal with the I-cache discrepancy between Cortex-A15 and Cortex-A7,
let's assume aliasing I-cache in both cases.
Note: this might need to be refined i.e. detect a big.LITTLE system
somehow by probing all CPUs not only the boot one.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
The cpuidle code requires SPC hardware, so check for its presence
before initialising. This enables the cpuidle code to safely exist
in kernels run on hardware without SPC support.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
TC2 test-chip integrates power management circuitry and firmware that
allows to remove voltage from both (A7 and A15) clusters when they are
idle or more generically when the system is forced into shutdown mode.
All CPUs in a cluster share the same voltage source so they cannot be
shutdown independently. In order to take advantage of TC2 power
management capabilities this patch implements a multi-cluster aware
CPU idle implementation. It is based on coupled C-state concept provided
by this code:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-April/097084.html
CPUs that are part of the same cluster are coupled using the mask
provided by the MPIDR at boot. Once all CPUs hit the coupled barrier the
primary CPU in the cluster (the one with MPIDR[7:0] == 0) waits for
secondaries to clean their L1 and enter wfi. Then it cleans all cache
levels, exits cluster coherency and starts the procedure to shutdown the
respective cluster. All wake-up IRQ sources are enabled by default.
Deep shutdown states for clusters are not enabled by default.
To enabled them:
A15 cluster
echo 0 > /sys/kernel/debug/idle_debug/enable_idle
A7 cluster
echo 1 > /sys/kernel/debug/idle_debug/enable_idle
Tested thoroughly using lookbusy to modulate system load and trigger idle
states entry/exit.
The patch "ARM: kernel: fix MPIDR cpu_{suspend}/{resume} usage"
uses the BFC assembler instruction but this isn't available
on ARMv6 CPUs, which breaks compilation when building kernels which
support both SMP and ARMv6, e.g. omap2plus_defconifg.
Fix this by using a BIC instruction instead.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
The current version of cpu_{suspend}/{resume} relies on the 8 LSBs of
the MPIDR register to index the context pointer saved and restored on
CPU shutdown. This approach breaks as soon as platforms with populated
MPIDR affinity levels 1 and 2 are deployed, since the MPIDR cannot be
considered a linear index anymore.
There are multiple solutions to this problem, each with pros and cons.
This patch changes cpu_{suspend}/{resume} so that the CPU logical id
is used to retrieve an index into the context pointers array.
Performance is impacted on both save and restore paths. On save path
the CPU logical id has to be retrieved from thread_info; since caches
are on, the performance hit should be neglectable. In the resume code
path the MMU is off and so are the caches. The patch adds a trivial for
loop that polls the cpu_logical_map array scanning the present MPIDRs and
retrieves the actual CPU logical index. Since everything runs out of
strongly ordered memory the perfomance hit in the resume code path must
be measured and thought over; it worsens as the number of CPUs increases
since it is a linear search (but can be improved).
On the up side, the logical index approach is by far the easiest solution in
terms of coding and make dynamic changes to the cpu mapping trivial at
run-time.
Any change to the cpu_logical_map (ie in-kernel switcher) at run time must be
cleaned from the caches since this data has to be retrieved with the MMU
off, when caches are not searched.
Tested on TC2 and fast models.
The functions in mcpm_entry.c are mostly intended for use during
scary cache and coherency disabling sequences, or do other things
which confuse trace ... like powering a CPU down and not
returning. Similarly for the backend code.
For simplicity, this patch just makes whole files notrace.
There should be more than enough traceable points on the paths to
these functions, but we can be more fine-grained later if there is
a need for it.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
This patch allows the vexpress 'rtsm' native backend to probe
the dt for presence of the psci backend. If present then the native
implementation of the 'bL_platform_power_ops' is not used.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Add the required code to properly handle race free platform coherency exit
to the DCSCB power down method.
The power_up_setup callback is used to enable the CCI interface for
the cluster being brought up. This must be done in assembly before
the kernel environment is entered.
Thanks to Achin Gupta and Nicolas Pitre for their help and
contributions.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
If 4 CPUs are assumed, the A15x1-A7x1 model configuration would never
shut down the initial cluster as the 0xf reset bit mask will never be
observed. Let's construct this mask based on the provided information
in the DCSCB config register for the number of CPUs per cluster.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
It is possible for a CPU to be told to power up before it managed
to power itself down. Solve this race with a usage count to deal
with this possibility as mandated by the MCPM API definition.
Signed-off-by: nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
This adds basic CPU and cluster reset controls on RTSM for the
A15x4-A7x4 model configuration using the Dual Cluster System
Configuration Block (DCSCB).
The cache coherency interconnect (CCI) is not handled yet.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
This patch adds the 'psci' kernel command line option. Secure firmware cannot
yet add a psci device node in the dt to indicate whether it supports psci or
not. So in the current dt, the psci device node is present by default. The
probe function will always indicate that the secure firmware implements psci
irrespective of the address space linux runs in as the same device tree will
be used in either case. Hence a kernel cmdline option is required to choose
either the native or psci power api backend depending upon the address space
linux is running in.
Specifying 'psci=enable' in the cmdline will allow Linux running in the
non-secure address space to use the same dt but use the psci backend instead
of the native backend. It effectively overrides the presence of the native
implementation by ensuring registration of the psci backend. Linux running in
the secure address space will use the native backend for power management when
'psci=disable' in the cmdline (also the default value i.e. psci backend is
disabled by default) or the psci node in the dt is absent.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
This patch adds a probe function to check if the secure firmware has an
implementation of the Power State Coordination Interface.
'bL_platform_power_ops' will be implemented by:
a. a native backend when Linux runs in secure world
b. a psci backend which relies on the secure firmware to implement the
power ops
presence of b. will be indicated by the psci device node in the device tree.
The device node is expected to be populated by the secure firmware if it
supports psci. If the native backend detects a psci node then it bails out
allowing the psci backend to be registered.
Also a dummy 'psci_probe' function is added for the case when psci support
is not included. This prevents the build from breaking for tc2 and the
rtsm platforms.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
This patch adds a possible error code of the cpu_on psci api. It
indicates that the cpu specified in the cpu_on call is up and running
(e.g. the firmware still has not seen the preceding cpu_off call).
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
The TC2 versatile express core tile integrates a logic block that provides the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power management. The logic block, called Serial Power Controller
(SPC), contains several memory mapped registers to control among other things
low-power states, operating points and reset control.
This patch provides a driver that enables run-time control of features
implemented by the SPC control logic.
The driver also provides a bridge interface through the vexpress config
infrastructure. Operations allowing to read/write operating points are
made to go via the same interface as configuration transactions so that
all requests to M3 are serialized.
Device tree bindings documentation for the SPC component is provided with
the patchset.
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
programming and retrieval. The helper that allocates the bridge functions
requires an additional parameter allowing to request component specific
functions that need not be initialized through device tree bindings but
just using simple look-up and statically defined constants.
This patch introduces the necessary changes to the vexpress config layer
to cater for the new vexpress bridge interface requirements.
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Achin Gupta <achin.gupta@arm.com>
Cc: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
CCI400 has a set of counters that can be used to profile different
transations at CCI master and slave interfaces. These counters can
observe different kinds of transations passing through the CCI and
provide a system-level view of activity.
This patch adds support for CCI PMU by extending the existing CCI
driver.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
This is a hack to enable the old CCI PMU patches to be used with the new
CCI driver. The CCI PMU is (mis)represented by a separate node in TC2
device-tree.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
This provides cci_enable_port_for_self(). This is the counterpart to
cci_disable_port_by_cpu(self).
This is meant to be called from the MCPM machine specific power_up_setup
callback code when the appropriate affinity level needs to be initialized.
The code therefore has to be position independent as the MMU is still off
and it cannot rely on any stack space.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Dave Martin <dave.martin@linaro.org>
On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to it.
This patch enables the basic infrastructure required in Linux to handle and
programme the CCI component.
Non-local variables used by the CCI management functions called by power
down function calls after disabling the cache must be flushed out to main
memory in advance, otherwise incoherency of those values may occur if they
are sitting in the cache of some other CPU when power down functions
execute. Driver code ensures that relevant data structures are flushed
from inner and outer caches after the driver probe is completed.
CCI slave port resources are linked to set of CPUs through bus masters
phandle properties that link the interface resources to masters node in
the device tree.
Documentation describing the CCI DT bindings is provided with the patch.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
