Add support gt9xx driver for Rockchip platform goodix
touchscreen.
There is a goodix driver on upstream but it not work well, so
use the old driver until someone debug the upstream driver.
Change-Id: Id8711a63150da4bdcd8e78f3b2a82157e1b3de4f
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
This makes dmc driver possible to register a system status notifier and
other drivers possible to call the notifier call-back easily, so that
the dmc driver can change frequency according to different system status.
Change-Id: I1a4fb4649366d75310d2e29f87775bb2d9ca3d67
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
In rockchip_clk_register_ddrclk,
ifdef CONFIG_ARM
if (!psci_smp_available())
return NULL;
endif
Add "__init" for rockchip_clk_register_ddrclk() to match with
psci_smp_available().
Change-Id: Ib6849e359921c3a937bf8dc4f6547aed353f1071
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
ARM32 system can run without trustos,
we should prevent arm_smccc_smc being called in such system.
Change-Id: Ic87b78107b464e3ab8dc72a3ca1fa9a64e358580
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Because uart does not have high requirements
for the clk Jitter, the fractional frequency
divider does not need to meet the 20-fold relationship.
(If uart clk rate < 24M,Use 24M as the fractional
clock source.)
Change-Id: I3f55f8a4ba5dc4c950c2742dc914c41e7b6e4ee6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Numerator is greater than 4,the clk jitter is better.
Change-Id: I9fda9ddeb7b26c6b8559b4126e2ad1d29bb850d1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
As npll rate may be changed according to vopl dclk rate on px30.
Change-Id: I4abc042b49ee06436ba5d69dc8adfa9460da37f7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
NPLL should provide clock for vopl dclk on px30, and its rate will be
changed according to vopl dclk rate, so GPU can't use npll as parent
on px30.
Change-Id: Ib2c8c57020405bcd14070dcd7bc71cbfe18230e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The bigger the divider, the better the clock jitter.
Change-Id: I4b4e06c71c2f0bdb0e32422fb42c8d490c3ec4bd
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Zero is a valid value for half-divider.
Change-Id: I23aa8afcd391da95396e5d808c3c424f993c66e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The div offset of some clocks are different from their mux offset
and the COMPOSITE clock-type require that div and mux offset are
the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle that.
Change-Id: I7d541e29328f37d2ad806b3b6e5ab35b5513b345
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
support fractional divider with only one level parent clock
Change-Id: I6593f908edf4454ef03255080bf9ac1d72c6f64e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
crypto and dmac share the same noc clk,
so mark the aclk_dmac1 as critical clk.
Change-Id: I34a4a7cc532a385086679fafb961a47b0a6abc3b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
crypto and dmac share the same noc clk,
so mark the aclk_dmac_bus as critical clk.
Change-Id: Ib0b70bbed3fdefeab7b6f2b5f88350a416e66787
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
