1. Add a new compatible for rk3399;
2. Support gpio operation for vbus-drv.
Change-Id: I2eb1ac377db0bcb907d009c56fba22f1951c128e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
On some systems regulators need to do special actions on suspend/resume.
These get set from the generic regulator_suspend_prepare and
regulator_suspend_finish functions so these should be called from the
psci suspend ops as well.
Change-Id: I6fbf7b39ceae936ed5bd9df6719ccd3cd360840f
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
RK3399 dwc3 has some hardware properties, which is platform
dependent, including the following properties:
1. Set PHYIF to 1 to use 16-bit UTMI+ interface;
2. Clear ENBLSLPM to 0 to disable sleep and l1 suspend;
3. Clear U2_FREECLK_EXITSTS to 0;
4. Clear DEV_FORCE_20_CLK_FOR_30_CLK to 0;
5. Clear DELAYP1TRANS to 0;
Change-Id: I85de326e3c2177c66966f1239bcab838df01492d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether delay PHY power change from P0
to P1/P2/P3 when link state changing from U0 to U1/U2/U3
respectively.
Change-Id: I23e33f8b13001d6f86d6473ad43a261d9bda8f79
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Fix add critical clock for PMUCRU too late in the rk3399_clk_init. It
will be crash if there is one clock want to disable its parent which is
the PPLL.
Change-Id: I3fa236ab78571c8c8ec5d423228d00dbb02f24e6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
this patch corrects the interface adc/dac control register definition
according to datasheet.
Change-Id: I0777577d365140b642141596112b662d3a80538b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org broonie/sound.git for-next
commit 653aa46452)
In order to lower the temperature, lower the voltage.
Change-Id: Iae2d103c88ab5b72c3d003c1f84f74e1694c7e1e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
PPLL is 8 and redefined by SCLK_I2C4_PMU, and clock IDs shouldn't be 0.
Change-Id: I50f89487034c1f1ef41d257de00b7f3ec53f7f4c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Add snps,phyif_utmi_16_bits devicetree property. USB2 phy
interface is hardware property, and it's platform dependent,
so we need to configure it in devicetree to set the core to
support a UTMI+ PHY with an 8- or 16-bit interface.
And according to dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must set to the required values for the usb2 phy interface.
Change-Id: If1c636edc6be3c9a79b4b0b89737a925d8dd3abe
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Change-Id: I84ea6eeccb9fc2ea6d13ef586f1166d5fa132606
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
* linux-linaro-lsk-v4.4-android: (477 commits)
arm64: vdso: Mark vDSO code as read-only
ARM/vdso: Mark the vDSO code read-only after init
x86/vdso: Mark the vDSO code read-only after init
lkdtm: Verify that '__ro_after_init' works correctly
arch: Introduce post-init read-only memory
x86/mm: Always enable CONFIG_DEBUG_RODATA and remove the Kconfig option
mm/init: Add 'rodata=off' boot cmdline parameter to disable read-only kernel mappings
asm-generic: Consolidate mark_rodata_ro()
Linux 4.4.6
ld-version: Fix awk regex compile failure
target: Drop incorrect ABORT_TASK put for completed commands
block: don't optimize for non-cloned bio in bio_get_last_bvec()
MIPS: smp.c: Fix uninitialised temp_foreign_map
MIPS: Fix build error when SMP is used without GIC
ovl: fix getcwd() failure after unsuccessful rmdir
ovl: copy new uid/gid into overlayfs runtime inode
userfaultfd: don't block on the last VM updates at exit time
powerpc/powernv: Fix OPAL_CONSOLE_FLUSH prototype and usages
powerpc/powernv: Add a kmsg_dumper that flushes console output on panic
powerpc: Fix dedotify for binutils >= 2.26
...
set clk_cpul:816M clk_cpub:1008M when clk tree init
Change-Id: I8f493ce8479fc670aa05d651db5be354d6870c98
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
With this defconfig which inherits from rockchip_defconfig,
ChromeOS boots up to command line.
Change-Id: I646fea9b26d9c235da16d0d2b559290ee5029a12
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
1. Compatible "rockchip,rk3399-usb-phy" support to RK3399;
2. Add host_drv_gpio optional property for usb2.0 vbus control.
Change-Id: Idfc6898ca2c519c46dae66d396f501b38e8d73bd
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
Change-Id: I116b66c3b417cfecc968414db9912813a0ef2c5d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
To make android platform iommu work well, we need a unified compatible
name to match the new iommu definition in dtsi
Change-Id: Ied581653e1261fd0a21577f4e9ce3b915af135cd
Signed-off-by: Simon <xxm@rock-chips.com>
The rk3288, rk3368 and rk3366 have the same physical dsi id 0x3133302A,
so do not need to get dsi host id.
Change-Id: I0de1e9b7c0250b37ffdc2c39155c5f16afb48956
Signed-off-by: xubilv <xbl@rock-chips.com>
Assign rates for aclk_bus and aclk_peri according to our original design.
Change-Id: Iab4961d485421151be5dbdacf6929800150ab342
Signed-off-by: Feng Xiao <xf@rock-chips.com>
add 1296MHz, 1104MHz and 216MHz to the cpuclk_rate_table list
Change-Id: I1ea7ee432b7c69b89cb3c11a74e67d9d6af1a5dd
Signed-off-by: Feng Xiao <xf@rock-chips.com>
For sheep board, we have decided to assign vop full for
use with HDMI. And we can also change it in the board
dts in the further.
Change-Id: Id966615c84cef50f0e8d849e3840434ba7f7b7ec
Signed-off-by: Feng Xiao <xf@rock-chips.com>
We will need a pll to support all kinds of clock rate requirement
for HDMI which may change the rate at run time.
In order not to affect other clocks, remove the npll from the
parent list of other clocks and only DCLK_VOP(FULL or LITE) can
select npll as parent. Also add the ability for DCLK_VOP to set
the rate of its parent (which is now forced to NPLL).
Change-Id: I1e13ef1c4f1b9728f9c173454d5056780c47a95e
Signed-off-by: Feng Xiao <xf@rock-chips.com>
