PD#SWPL-11314
Problem:
When playing profile 4, multiple resolution and dual layer dv
streaming, switching non-4k to 4K (DOVI->SDR), need do once
control path reset since the core1 setting is not correctly.
Solution:
Improve the condition to reset control path
Verify:
Verified on AC211
Change-Id: I229a33228377bd9ff7811b4a25e973eeba8af66d
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
PD#SWPL-7987
Problem:
TL1 DRM support
Solution:
add TL1 DRM support
Verify:
t962x2_x301
Change-Id: Ibc8ff641f42c0a416e80c3a420c1d808e0ad8b26
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>
PD#TV-8725
Problem:
STR standby, wake up, takes a long time, takes 5-6s.
Solution:
When the first frame is displayed,
the statistics start new frame count.
Verify:
Verified with X301
Change-Id: Ib318455959fe9688f3c697b1d562388547002877
Signed-off-by: Rui Wang <rui.wang@amlogic.com>
PD#SWPL-13223
Problem:
there is a white line on left when crop left is odd
Solution:
set post mif phase to 8;
Verify:
TL1
Change-Id: Ic39e15f5c1d07e756ecc4909366af35d1472dc29
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#SWPL-13223
Problem:
when crop left is odd, the video has white edge
Solution:
if vframe not processed by di,
set vd mif chroma init hphase to 8 when h crop start is odd
Verify:
verify on T972
Change-Id: Ica57503e6eebd57972129513304ae39b445ccf77
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
PD#SWPL-11059
Problem:
gamma setting in DRM
Solution:
merge commit related to gamma
Author: Ao Xu <ao.xu@amlogic.com>
Date: Tue Oct 30 19:18:21 2018 +0800
drm: add meson private property gamma_lut
When setting CTM, gamma is also set again.
Setting gamma frequently will lead to visual glitches.
Add a private value to record whether
gamma_lut blob is changed.
Bug: b/113682067
Test: Ran on device and changed gamma to verify there are no glitches
Author: Fergus Simpson <afergs@google.com>
Date: Fri Aug 10 13:18:36 2018 -0700
[Estelle] Enable top/bottom color clamping
Modifies amvecm's color clipping to allow either the lower or upper
limit to be set. This sets clipping registers that hold the top and
bottom 10-bit clipping values for each color channel.
This does not cause the artifacts that we've been seeing while trying
enable the gamma tables.
Usage (set a clip of 32/255):
echo 20080020 > /sys/class/amvecm/color_bottom
Bug: 109942195
Test: Flashed to device and tested with a internal changes that use the
registers.
Author: Frank Chen <frank.chen@amlogic.com>
Date: Wed Aug 8 15:21:17 2018 +0800
remove gamma_enable in am_meson_crtc_create
Verify:
verify by u200
Change-Id: I4221b3b4671516e7afd4dea14ce3cd71b4b66433
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>
PD#SWPL-13130
Problem:
on LG UBK80-N DVD, hdcp22 auth passed before esm reset,
auth status will be reset, result in black screen
Solution:
delay hdcp22 auth to after esm reset
Verify:
TXLX
Change-Id: I4e7fe60cf3117712eea5f8b1eec65d544b557a48
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
PD#SWPL-12382
Problem:
active hdmitx clk will cause cvbsout clk cleared by bl30 auto limitation
Solution:
disable hdmitx clk when vout disable hdmitx
Verify:
p281
Change-Id: Ie9da30173d682901e9160a0db9c775c204a770f9
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
PD#SWPL-12972
Problem:
vdin regs has been set to default when entering suspend.
Solution:
don't set regs since upper layer will not start again after resume.
Verify:
verified by t962x2_x301
Change-Id: Ic1042e0b1a9ba4482fe79c51606e366f60e31f59
Signed-off-by: zhiwei.yuan <zhiwei.yuan@amlogic.com>
PD#SWPL-12849
Problem:
Update meta and el function was called incorrectly. It
will cause the BL and EL mismatch.
Solution:
Correct the calling sequence to get correct EL frame
Verify:
Verified by AC211
Change-Id: I6c9f0221a9facd361fcd18dcda55cc3967593c1c
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
PD#SWPL-9266
Problem:
Using line int rdma will randomly cause dv/hdr register setting
incompleted during one vsync.
Solution:
Disable line int rdma operation. Always enable dv/hdr core
for osd.
Verify:
Verified on galilei revb
Change-Id: I8622896ab0432ef3d9db843aa5ab6d06168aad2a
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
PD#SWPL-13177
Problem:
stop endpoint race
Solution:
A counter was used to find out if the stop endpoint completion raced with
the stop endpoint timeout timer. This was needed in case the stop ep
completion failed to delete the timer as it was running on anoter cpu.
The EP_STOP_CMD_PENDING flag was not enough as a new stop endpoint command
may be queued between the command completion and timeout function, which
would set the flag back.
Instead of the separate counter that was used we can detect the race by
checking both the STOP_EP_PENDING flag and timer_pending in the timeout
function.
Verify:
franklin
Change-Id: Ie958ffd530a6bd176d0cf451894a5bd4dece38da
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
PD#SWPL-12722
Problem:
Previously, disabled the SR function when DV on. Since we want
to pass the dv certification without any external flag setting.
But it will affect the PQ function in SR after g12a.
Solution:
Just enable SR function under DV on. Only disable it under
certification mode.
Verify:
Verified on u212
Change-Id: I01bb8cad3fd48246f5af884f84dcc280f85908a1
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
PD#SWPL-12424
Problem:
run hs400 166M on sm1 now
Solution:
modify dts
Verify:
passed on sm1_ac200
Change-Id: I28f5f8da3481c9f2a19e27bc8e430a3379ec6b2a
Signed-off-by: Ruixuan Li <ruixuan.li@amlogic.com>
PD#SWPL-12461
Problem:
standby power consumption is too high
Solution:
1.when standby set spdif pin low
2.when standby set GPIOAO_2 low
Verify:
verify by U212
Change-Id: I29699688288b0e09529b7a35a4559ff1fad9891e
Signed-off-by: jiejing.wang <jiejing.wang@amlogic.com>
PD#SWPL-392
Problem:
black screen 1s during kernel boot at 4k30hz.
The reason is vic is 0.
Solution:
Init vic when hdmi init.
Verify:
G12A
Change-Id: I0e055ddb1fcd9ee4c7bc009c9160176a0c101d8b
Signed-off-by: yao liu <yao.liu@amlogic.com>
PD#SWPL-392
Problem:
transition from uboot to kernel is not smooth
Solution:
enable DV output in uboot and kernel check if
dolby enabled in uboot
Verify:
G12B/G12A
Change-Id: I7f310794cf18a54c15a6f059c460e8dcdf9c25aa
Signed-off-by: yao liu <yao.liu@amlogic.com>
PD#TV-9100
Problem:
1.optimize calls with other modules.
Solution:
1.optimize calls with other modules.
2.add ext file interacts with other modules.
3.add sync to prevent NULL pointer crashes.
Verify:
Verified by x301
Change-Id: Id1930400454b020616e0c669cae5f473f498b6de
Signed-off-by: nengwen.chen <nengwen.chen@amlogic.com>
PD#SWPL-12404
Problem:
red and green stripes dividing line flash black line
Solution:
close cue(422/444) except local play(420)
VLSI-yanling suggest
Verify:
TL1
Change-Id: Ied1554d6a0e64e00aea1e692ab6b405f87387095
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#SWPL-12778
Problem:
atv signal can't recover after hot plug cable
Solution:
update snow playing nosig state
Verify:
x301
Change-Id: I143ca203c60e5090d41e543306f3929b4544af0c
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
PD#SWPL-11320
Problem:
current gem driver have not implementted the import interface.
For drm-hwc in android, gralloc allocate the dumb buffer, it
should use the import interface to import the allocated buffer
to the drm driver.
Solution:
implement the gem import interface
Verify:
g12a-u200
Change-Id: I32f7705fd67853a1000875b2af69fcaf700330e1
Signed-off-by: Ao Xu <ao.xu@amlogic.com>
PD#SWPL-12289
Problem:
drm driver has no debug sysfs file
Solution:
add follow sysfs node
1. dump the osd register
/sys/kernel/debug/dri/%minor%/vpu/reg_dump
2. dump the gem buffer image
/sys/kernel/debug/dri/%minor%/vpu/dump
3. set the gem buffer image store path
/sys/kernel/debug/dri/%minor%/vpu/imgpath
4. set 1 to disable the osd plane
/sys/kernel/debug/dri/%minor%/vpu/blank
Verify:
g12a-u200
Change-Id: I10746d65b09d3b530dc22720b8cee669fa120dde
Signed-off-by: Ao Xu <ao.xu@amlogic.com>
PD#SWPL-13092
Problem:
drm driver has no drm support
Solution:
add afbc block support
Verify:
g12a-u200
Change-Id: If2e57b63032e9f93be800bda652b80e560163231
Signed-off-by: Ao Xu <ao.xu@amlogic.com>
PD#TV-8696
Problem:
DMC can't set up from bootargs. For easy debug, we need
set a monitor from bootargs.
Solution:
Add a funciton for this feature. You can using following patten
to set up a DMC monitor:
dmc_montiro=[start_addr],[end_addr],[mask]
Example:
setenv initargs $initargs dmc_monitor=0x0,0x20000000,0xff58
This command set up monitor for following device on GXL:
RANGE:0 - 20000000
MONITOR DEVICE:
HDCP
HEVC
USB3.0
VPU READ1
VPU READ2
VPU READ3
VPU WRITE1
VPU WRITE2
VDEC
HCODEC
GE2DV
Verify:
P212
Change-Id: I864ff97325981fe62f18a4a4a24700b6b6ea7482
Signed-off-by: Tao Zeng <tao.zeng@amlogic.com>
PD#SWPL-12885
Problem:
incorrect bin num of cm histogram
Solution:
have the value reflect register
spec correctly
Verify:
TL1
Change-Id: I77088cae29d716228c80fb31462585fdf67f34d9
Signed-off-by: Xihai Zhu <xihai.zhu@amlogic.com>
PD#TV-8378
Problem:
shutdown test for hdmiin, sometimes audio is silence.
Solution:
if hdmiin is unsatble, set default resample to 48K
Verify:
X301 T972
Change-Id: I31acc38772006646176092968eb23628e23dbaf7
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
PD#TV-8460
Problem:
ATV str test is stucked
Solution:
disable some audio print messages
Verify:
Verfied on marconi
Change-Id: I284c8afde3a6bc9ff3b8ebfe19360abbb152c3f8
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
PD#SWPL-9137
Problem:
tl1 add APIs to control pixel probe for debug
Solution:
tl1 add APIs to control pixel probe for debug
Verify:
X301
this commit MUST not be merged into trunk!!!
Change-Id: I3a538ff3afdd80ef5669fac63a3ab5f43b8e1055
Signed-off-by: Yan Wang <yan.wang@amlogic.com>
PD#SWPL-12867
Problem:
after some swtich or on/off operation, minor block
artifect is seen under super black pattern
Solution:
improve the temporal filter calculation and fine tune
related parameter as well
Verify:
TL1
Change-Id: If52360e458934d71438899b88d9246f1279ce524
Signed-off-by: Xihai Zhu <xihai.zhu@amlogic.com>
PD#SWPL-12922
Problem:
the lcd display abnormal
Solution:
do not disable tcon clock,add
CLK_IGNORE_UNUSED flag for tcon clock
Verify:
tl1
Change-Id: If2ac02670c58a21604ce2a36ae353ceddd5ecae5
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-12753, PD#TV-8736
Problem:
ft had change the Max range to 4.8G, so adc pll can't
over than 4.8 Ghz.
Solution:
modify pll default setting
Verify:
tl1
Change-Id: I9f489300762f653f967e8c2219c79882236062ab
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
PD#SWPL-10064
Problem:
add di-multi folder
Solution:
1. add di_multi folder;
2. it can be enable by dts;
3. only one of di can be enabled at the same time;
4. no di-pq filse;
Verify:
U212
Change-Id: I8726d2430cf1beb58d0cd37c0358b7ea8e06c414
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#TV-7783
Problem:
fix non-standard signal.
Solution:
1.fix non-standard signal when channel scanning and playing.
2.disable demod afc when enable non standard.
Verify:
Verified by x301
Change-Id: I177e6eb5388e554e3166a65e23e3b7bdefac3e97
Signed-off-by: nengwen.chen <nengwen.chen@amlogic.com>
PD#TV-8401
Problem:
Customer needs to access spi nor by the spicc.
Solution:
add spi nor interfaces in spicc driver.
add gd25q80c/FM25Q08A surpport
Verify:
tl1 x301
Change-Id: If94858d46c31fea6b37034a8b1dfe94a9e9f4603
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
