Since we needs to delay ~1ms to wait for 480MHz output clock
of USB2 PHY to become stable after turn on it, the delay time
is pretty long for something that's supposed to be "atomic"
like a clk_enable(). Consider that clk_enable() will disable
interrupt and that a 1ms interrupt latency is not sensible.
The 480MHz output clock should be handled in prepare callbacks
which support gate a clk if the operation may sleep.
Change-Id: I943e17f8a97d1229fefd8c1ada706e0c450c98eb
Signed-off-by: William Wu <wulf@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
this patch add support for i2s bclk fs configuration, we can
configure bclk_fs by devicetree as required.
Change-Id: I7e034e0466793b5b9eab6566a43e90213f219bb0
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
some device will triggered hpd after dp is connected, so we don't do
traning if dp lanes is not changed.
Change-Id: I3e329e7d2db33138f283ad6584b966ebd0619f65
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
This patch create host_testmode file in debugfs for
USB HOST. It's useful for us to use a scope to verify
signal integrity for USB2/USB3 HOST.
For example， set testmodes for RK3399 board USB:
1. set Test packet for Type-C0 USB2 HOST:
echo test_packet > /sys/kernel/debug/usb@fe800000/host_testmode
2. set compliance mode for Type-C0 USB3 HOST normal orientation:
echo test_u3 > /sys/kernel/debug/usb@fe800000/host_testmode
3. set compliance mode for Type-C0 USB3 HOST flip orientation:
echo test_flip_u3 > /sys/kernel/debug/usb@fe800000/host_testmode
4. check the testmode status:
cat /sys/kernel/debug/usb@fe800000/host_testmode
The log maybe like this:
U2: test_packet /* means that U2 in test mode */
U3: compliance mode /* means that U3 in test mode */
Change-Id: Ic7e464b0443c792848846246b782ffba30bf2120
Signed-off-by: William Wu <wulf@rock-chips.com>
The returned value of topology_physical_package_id is socket id
on ARM32 system(for example, RK3288), it's not like the cluster id
on ARM64 system(for example, RK3366), so use a new way.
Change-Id: I5b2cdfdcdaa56c71df394caa2588f6e83931a293
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The sequence got a bit wrong as we are sending CPUFREQ_START
notifications even before we have sent CPUFREQ_CREATE_POLICY.
Fix it.
Change-Id: I7d1fba317314bb5e5601b1354494398def156424
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
(cherry picked from commit 388612baba)
shift the time of vbus enable before attach debounce started,
and merge the code of get_cc from chrome ec driver, which used
to fix connection disconnected issue.
Change-Id: I2fd1f83d0265b3770d75a59d622d0f650d737c5b
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
It would be better to name OPP nodes as opp@<opp-hz> as that will ensure
that multiple DT nodes don't contain the same frequency. Of course we
expect the writer to name the node with its opp-hz frequency and not any
other frequency.
And that will let the compile error out if multiple nodes are using the
same opp-hz frequency.
Change-Id: I8c77646329e39390fb135d4d75d34893a8168876
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Do dptx/apb/core reset on every dp clock enabling, otherwise dp
will fail to load the firmware sometimes.
Change-Id: Ied0caad99d865ec86162dead2b4769a53f8db12a
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
Make sure drivers work if rk_keys do not selected.
Change-Id: I2882e6c69f0ddbff54089f824be33964ded3cb2e
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Right now only one driver support vpu and rkvdec,
so move the nodes from rk3399-android[-next].dtsi to rk3399.dtsi.
Change-Id: Id908843774ed8eede3aeddb24059ae92a35e5b98
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
This driver is modified to support RK3328 SoC.
RK3328 SoC is only support idle.
add DOMAIN_M type, for support regs have write_enable bit.
Change-Id: I5780b7bab680ddd9d9480e19d7c49681dd571d27
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add binding documentation for the power domains
found on Rockchip RK3328 SoCs.
But RK3328 SoC just support idle, not support pd.
Change-Id: I331680b2e91a45fd09f4bdab7ff9fd3990cb35c4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
According to a description from TRM, add all the idle request.
Change-Id: Ia2fdb20d89f7e668a3c86074ebed8c73ab0a9429
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
due to function will be called from rk_headset_irq_hook_adc.c
when es8316 configured in defconfig file but not in device tree
Change-Id: Ie0294fff2c05b9f77c6740d81dc9445007c1b62b
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
We could find the external abort for trying to access
nvme's BAR space to check the csts, but it's possible
that the link state is forbidden to access the BAR when
failing to reset it. So we should reuse the former csts
to print the log instead of doing that again.
Change-Id: I34438a726381e588eb21149b1aab76a66ef0e665
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
When dwc3 core enters into suspend mode, the PD may turn off
for power saving, which will cause dwc3 controller lost the
mode operation when resuming time.
This adds redo the mode setting into dwc3_core_init() function
to avoid this issue.
BUG=Redmine: Defect#110481
TEST=rk3399-sapphire-excavator-box(CVTE), check if USB3.0 HUB
can be enumerated after PM resume.
Change-Id: I61c512e9c368afc665cd4d5900367079ed22a34e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Usb-controller can invoke phy_power_on/off in its suspend/resume
process, so usb-phy need not do it again.
This adds remove phy_power_on/off in its suspend/resume cases.
Change-Id: Ice30e79ffba8116ca9bfae344c7ea232f6580130
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
