Indeed, the values of the model parameters are supplied by Rocky Hao.
Change-Id: I23edaa0ee104d07f79f5bf5bdbd393b4fb3c5120
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
Indeed, the values of the model parameters are supplied by Rocky Hao.
Change-Id: Ie6ff535eab3a1fabcd69289a0c1f32c76603a391
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
If sink max TMDS clock < 340MHz, we think the mode pixel clock
greater than 340MHz should support YCbCr420, or it is a bad mode.
Change-Id: I9f53fa4f9875977ae0355b65d9ccd8a304558c5d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Add dfi and dmc nodes in the device tree for the ARM rk3288 SoC.
To support ddr frequency scaling function, we need enable dmc and
dfi nodes.
Change-Id: Ib796c08c694e74e0da3319d2797e95aecf3e7e73
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
This makes ddr possible to enter auto self-refresh mode
when early suspend.
Change-Id: I0cd214bcb9c8e82aeea3f335a77be21feb356e2d
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
The current EDID might not support advanced HDMI 2.0 features.
Leaving old hdmi info in the drm_display_info will make display
work not okay, when switching display from HDMI 2.0 device to
HDMI 1.4 device.
Change-Id: Ifaf11a115580a93ec00160d54f0d453842d7b484
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch use one cpudai->multicodecs card for built-in hdmi and
external codec which share the same i2s controller.
Change-Id: Ib56d7f10b6739b1c26ec8946470b9f0cd7215979
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch enable SND_ROCKCHIP_HDMI_ANALOG for built-in hdmi sound
and external codec which share the same i2s controller.
Change-Id: I3ac29ba12f75c938e015d2b77a3b749888c2e4c2
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
when boot and resume,the fw should load/reload,this will take up
much time in the main thread,so here add a thread to load/reload
fw in order to void this situation.
Change-Id: Ic1a67fd662b0406ede08b0aeb944525fabc519e6
Signed-off-by: buluess.li <buluess.li@rock-chips.com>
tsadc in rk3288 can not work well at 10k hz clock. at most time, tsadc
in rk3288 can work well, but it will wrongly report a very high
temperature (eg. 110 degree) occasionally. we set 5k hz can
resolve this issue.
Change-Id: I06a4a1631baa5f65786a524e2430bb2386f52bdf
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
This reverts commit 6e9aa006c4.
UPSTREAM code has support parsing HDMI.20 HF-VSDB.
Change-Id: Ia25ee6a92e9a2fee4b3356446c1198e938c5e74d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch does following:
- Adds a new structure (drm_hdmi_info) in drm_display_info.
This structure will be used to save and indicate if sink
supports advanced HDMI 2.0 features
- Adds another structure drm_scdc within drm_hdmi_info, to
reflect scdc support and capabilities in connected HDMI 2.0 sink.
- Checks the HF-VSDB block for presence of SCDC, and marks it
in scdc structure
- If SCDC is present, checks if sink is capable of generating
SCDC read request, and marks it in scdc structure.
V2: Addressed review comments
Thierry:
- Fix typos in commit message and make abbreviation consistent
across the commit message.
- Change structure object name from hdmi_info -> hdmi
- Fix typos and abbreviations in description of structure drm_hdmi_info
end the description with a full stop.
- Create a structure drm_scdc, and keep all information related to SCDC
register set (supported, read request supported) etc in it.
Ville:
- Change rr -> read_request
- Call drm_detect_scrambling function drm_parse_hf_vsdb so that all
of HF-VSDB parsing can be kept in same function, in incremental
patches.
V3: Rebase.
V4: Rebase.
V5: Rebase.
V6: Addressed review comments from Ville
- Add clock rate calculations for 1/10 and 1/40 ratios
- Remove leftovers from old patchset
V7: Added R-B from Jose.
V8: Rebase.
V9: Rebase.
V10: Rebase.
Change-Id: I14d2a5585a528b7195170a4202be87199eb858c6
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-5-git-send-email-shashank.sharma@intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from 62c58af32c)
This patch does following:
- Adds a new structure (drm_hdmi_info) in drm_display_info.
This structure will be used to save and indicate if sink
supports advanced HDMI 2.0 features
- Adds another structure drm_scdc within drm_hdmi_info, to
reflect scdc support and capabilities in connected HDMI 2.0 sink.
- Checks the HF-VSDB block for presence of SCDC, and marks it
in scdc structure
- If SCDC is present, checks if sink is capable of generating
SCDC read request, and marks it in scdc structure.
V2: Addressed review comments
Thierry:
- Fix typos in commit message and make abbreviation consistent
across the commit message.
- Change structure object name from hdmi_info -> hdmi
- Fix typos and abbreviations in description of structure drm_hdmi_info
end the description with a full stop.
- Create a structure drm_scdc, and keep all information related to SCDC
register set (supported, read request supported) etc in it.
Ville:
- Change rr -> read_request
- Call drm_detect_scrambling function drm_parse_hf_vsdb so that all
of HF-VSDB parsing can be kept in same function, in incremental
patches.
V3: Rebase.
V4: Rebase.
V5: Rebase.
V6: Rebase.
V7: Added R-B from Jose.
V8: Rebase.
V9: Rebase.
V10: Rebase.
Change-Id: I93cd26ee5c51c3714eb702e8a1bd1b335385f26e
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-4-git-send-email-shashank.sharma@intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit afa1c76365)
The judgment condition of curr_ctrl is curr_ctrl->mpixelclock. It is
a hand mistake of commit <594a077e31e8b1ff0bd192e9af702fecaeea31ba>,
when patch(https://patchwork.kernel.org/patch/9603303) is merged.
Change-Id: I40b150e4f166aa4ca05c078f52347764bdd1fd01
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
if there not config CONFIG_FB_ROCKCHIP that will build error
Change-Id: Icaa837f3c0a539e98133b7cb9550700e8a46817f
Signed-off-by: buluess.li <buluess.li@rock-chips.com>
The judgment condition of pll_config is phy_config->mpixelclock. It is
a hand mistake of commit <594a077e31e8b1ff0bd192e9af702fecaeea31ba>.
Change-Id: I7e312fd3b7982ca4fdf610e577776bc5a45c4bde
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
The decoder requests the power domain is idle status when
it is resetting. Without the power domain it won't work.
Change-Id: If3afdbefbe40bc7529f13c12444adddbb328a21b
Signed-off-by: Randy Li <randy.li@rock-chips.com>
support rk3328 cvbs.Some display parameter can be configured,
such as saturation.For more information, please check
Documentation/devicetree/bindings/display/rockchip/rockchip_drm_tve.txt
Change-Id: Ifcc074a34910b58a26fc309fc601494562851025
Signed-off-by: algea.cao <algea.cao@rock-chips.com>
Only 200MHz, 300MHz, 400MHz, 528MHz, 600MHz, 666MHz, 732MHz and
800MHz are available at present.
Change-Id: I48ed7e6e6f636389fbc239b1cca201f5c5f19d7a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This makes it possible to enter ddr self-refresh mode
when early suspend.
Change-Id: Ib72f391af00674a3c3ab32bbbd4e4a857d3354e8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This registers a reboot notifier, it will change ddr frequency to a
specified value when reboot system.
This registers a fb notifier, it will change ddr frequency to a specified
value and enable ddr self-reflash mode when early suspend.
This adds a new sysfs node system_status, so that different system status
can change ddr frequency through the node.
Change-Id: Ib5d7d5bd8ee82c29f6f260a3d2ffcb829dde2003
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This makes dmc driver possible to register a system status notifier and
other drivers possible to call the notifier call-back easily, so that
the dmc driver can change frequency according to different system status.
Change-Id: I1a4fb4649366d75310d2e29f87775bb2d9ca3d67
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
On RK3328, dw-hdmi driver is reloaded after bind and unbind
then it will use the first register debugfs address if no run
debugfs_remove_recursive, and cause system crash.
Change-Id: Iafa6b4059962b62c79157a9cf6c3e1d56df48f03
Signed-off-by: xuhuicong <xhc@rock-chips.com>
In order to be able to use more than 4GB of RAM when the LPAE is
activated, the dts must be converted in 64 bits.
Most of the changes by the following commands:
sed -e 's/0xff/0x0 0xff/g' -e 's/0x0 0xff[[:xdigit:]]\{6\}/& 0x0/g'
sed 's/reg = <0x0 0x80000000>/reg = <0x0 0x0 0x0 0x80000000>/'
sed 's/reg = <0 0x80000000>/reg = <0x0 0x0 0x0 0x80000000>/'
sed 's/reg = <0 0x8000000>/reg = <0x0 0x0 0x0 0x8000000>/'
Change-Id: Ic4711ae04abc03db9ee09f78223a955a66a85d60
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Now OP-TEE OS can run in muti-core state,
so don't need switch to cpu0 anymore.'
Change-Id: I4f61120250823d6e2e13e2edeee58c26a184b7d2
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
