Commit Graph

593795 Commits

Author SHA1 Message Date
Shawn Lin
413ec720f5 Documentation: bindings: add more configuration for rockchip emmc phy
This patch add some optional configuration for dt. freq-sel can be used
to decide the phy sample clk in order to match the real freq of emmc
controller. dr-sel can be configured to match the requirement of different
drive strength of phy IO. opdelay should be used to adjust the output
delay for clk IO and data IO, which is useful for sloving timing issue.

Change-Id: I0b4da111581c76fbb96b15cd6be653aaa4843c33
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2016-04-25 17:57:31 +08:00
Shawn Lin
d1613edc35 phy: rockchip-emmc: add some setup configuration
Let's expose the freq-sel, dr-sel, opdalay to dt for user
to decide how to configure their phy.

Change-Id: Ib9ef40b263d3fd669c7bbda666d28c0c55ff6d8e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2016-04-25 17:56:45 +08:00
Douglas Anderson
6c4113f686 ARM64: dts: rockchip: Tiny comment cleanups for kevin-r0
I was having a hard time figuring out where to put new things in
kevin-r0.  Add some comments to explain the sort order.

BUG=None
TEST=Build and boot

Change-Id: I9fb8c200f934542ebed984566bab039d4ec3fd13
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256509
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Brian Norris <briannorris@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-04-25 16:02:41 +08:00
Douglas Anderson
8d3a4374ee ARM64: dts: rockchip: Remove 'veyron' in kevin/gru compatible
Veyron was an rk3288 board.  Having it in the compatible doesn't make a
ton of sense.  We'll stick 'gru' in the kevin name, though, since that
sorta makes sense.  Not that we ever really fall back to this stuff.

BUG=None
TEST=Build and boot

Change-Id: Ia4b6e02bd9b160c0b20e5459ca441047add2c0bd
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256508
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Brian Norris <briannorris@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-04-25 16:02:14 +08:00
Douglas Anderson
a26d116168 ARM64: dts: rockchip: Fixup revisions for kevin
Turns out that we got mixed up.  Old stuff should just be rev 0.  New
stuff should be rev 1+.  Fix all that.

BUG=None
TEST=Boot rev 0.

Change-Id: I41b38893f1e4224df4e3646cd268179307b3476b
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256507
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Brian Norris <briannorris@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-04-25 14:41:08 +08:00
Stephen Barber
eb8a871c2c arm64: dts: add kevin r1 and r2
Some pinctrl stuff has moved around and will be identical between gru
and kevin going forward, so kevin r1-specific things will be stored
in the kevin-r1 dts file.

BUG=none
TEST=kernel still boots on kevin-r1

Change-Id: If3e88a57acc40367afca34b5310a59efd70287f6
Signed-off-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256345
Commit-Ready: Stephen Barber <smbarber@google.com>
Tested-by: Stephen Barber <smbarber@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-04-25 14:39:35 +08:00
Brian Norris
8fedd9d578 FROMLIST: mfd: cros_ec: Allow building for ARM64
There are platforms using the ChromeOS embeded controller on ARM64 now,
so let's allow using this driver (without having to use COMPILE_TEST).

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

BUG=none
TEST=make sure we can enable cros_ec for ARM64

Change-Id: I828fec4a2022ea50f10c269ee88ae92c30f48337
Reviewed-on: https://chromium-review.googlesource.com/339540
Commit-Ready: Dan Shi <dshi@google.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Guenter Roeck <groeck@google.com>
Reviewed-on: https://chrome-internal-review.googlesource.com/256311
Commit-Ready: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-04-25 14:38:27 +08:00
Guenter Roeck
56ad960082 FROMLIST: platform/chrome: cros_ec_dev - Populate compat_ioctl
compat_ioctl has to be populated for 32 bit userspace applications to work
with 64 bit kernels.

BUG=chrome-os-partner:52276
TEST=Build and test with ectool on kevin

Change-Id: I3955d4cf869e4ad4b9f48cdc3b5901cf49dbbe83
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
(am from https://patchwork.kernel.org/patch/8844321/)
Signed-off-by: Guenter Roeck <groeck@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256310
Commit-Ready: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-04-25 14:38:00 +08:00
Stephen Barber
7229de675c ARM64: dts: gru: fix pwm regulator supplies
The vin-supply binding is valid only for fixed regulators. pwm-supply
should be used for PWM regulators.

Change-Id: I6b65eac6ddc424bb97ba9133b0d67286252b8568
Signed-off-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/255731
Tested-by: Stephen Barber <smbarber@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
2016-04-25 13:43:16 +08:00
Yakir Yang
62b22bf6a9 Revert "ARM64: dts: rk3399: gru: Let VOP Big first to select connector device"
We must not to adjust the port order, cause the port id is mapping
to VOP type. Current driver just hardcode that VOP Lit is ID 0, and
VOP Big is ID 1.

        ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
        if (ret)
                val = dp->data->lcdsel_lit | dp->data->lcdsel_mask;
        else
                val = dp->data->lcdsel_big | dp->data->lcdsel_mask;

Besides eDP could work well with VOP Lit, so we need to revert this
hack. Just revert commit 602f4f79c8.

Change-Id: I69badf2860c83c8211ea23b9f490fd4837dcf22e
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-25 11:23:14 +08:00
chenzhen
731680726b ARM64: dts: rk3399: gpu: add subnode for mali-simple-power-model
Change-Id: I0bd03634631ed30556cc45455582b075692cceba
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
2016-04-22 19:21:17 +08:00
Yakir Yang
30462103cc drm/rockchip: analogix_dp: Hack the vop out mode for RK3399 chip
For RK3999 chip, VOP Big/Lit must configure different display out
mode for eDP controller.
  - VOP Lit should output RGB888
  - Vop Big should output RGB10

Change-Id: I85bac6c25a990404682483c62a731681d19eca29
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-22 17:58:54 +08:00
Yakir Yang
d7b965329c drm/rockchip: analogix_dp: distinguish chip type for each chips
Driver could check the chip type to do some special things.

Change-Id: I2a33da466db0aa5133868c200a122df675f4c925
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-22 17:58:53 +08:00
Yakir Yang
3fa3bcc35c drm/rockchip: analogix_dp: rename analogix_dp_data to rockchip_dp_chip_data
Make the data structure name more exactly.

Change-Id: I3d7826ef86d2059cd1557bf4d31b7281377e9fae
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-22 17:58:52 +08:00
Yakir Yang
5ddac1b583 drm/rockchip: analogix_dp: remove the devtype check in .mode_valid function
The device type would always be ROCKCHIP_DP, so no need to add the
unused devtype check.

Change-Id: I7668a4bdb29700c5397583b9539446f19ae49c3b
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-22 17:58:52 +08:00
Yakir Yang
c5f989fbcd drm: bridge: analogix_dp: rename RK3288_DP to ROCKCHIP_DP
Change-Id: I05adaad81ea1beabee1fa674bc00f4e044a58913
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-22 17:58:51 +08:00
chenzhen
4c1a95df70 MALI: rockchip: update mali-midgard binding doc
Change-Id: Iffb05ab0032bf0be33652803d4931018e06e0631
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
2016-04-22 16:10:26 +08:00
chenzhen
c2ce740bf6 MALI: rockchip: adjust code about thermal for kernel 4.4
Change-Id: Ic5f3947b032deaaa800ee316636a8cc61259ba5d
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
2016-04-22 15:50:06 +08:00
Elaine Zhang
e6b6ba524b ARM64: rockchip_defconfig: enable pwm regulator
Change-Id: Id46711f5fd2de5b85e380c146ed77682aaae5376
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2016-04-22 15:48:00 +08:00
Adam Thomson
4b0140a236 UPSTREAM: ASoC: da7219: Disallow unsupported 32KHz clock setting in set_dai_sysclk()
The PLL function was updated to disallow 32KHz in
commit 501f72e9c5 ("ASoC: da7219: Remove support for 32KHz PLL mode"),
but set_dai_sysclk() was missed and still permits it. This patch resolves
that discrepancy.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org kernel/git/broonie/sound.git
topic/da7219 commit fb137ba64a)

Change-Id: I1cf8242745f39ac5ae3cb1aa30989bf4ab8f7f93
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-04-22 12:03:11 +08:00
Adam Thomson
f4fa97090e UPSTREAM: ASoC: da7219: Update PLL ranges and dividers to improve locking
The expected MCLK frequency ranges and the associated dividers
are updated to improve PLL locking in a corner scenario, with low
MCLK frequency near an input divider change boundary.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org kernel/git/broonie/sound.git
topic/da7219 commit 63a450aa4d)

Change-Id: I7b830ef2ea1e25600365872802924f617b6e0274
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-04-22 12:02:31 +08:00
Yakir Yang
a34e12b9f0 ARM64: dts: rk3399: evb1-cros: disabled eDP device node
There is a pull up resistor connected to eDP HPD pin on EVB1
hardware, and then eDP controller would always reported that
eDP panel is connected, even if no panel connected.

That would cause driver keep failed on eDP AUX communication,
and lots of annoying error messages would be printed out.

Beside actually the primary panel on EVB1 board is MIPI panel,
few people would have the eDP panel. So let's just disabled
the eDP device on EVB1 board.

Change-Id: Ic2f8b94360821f91e3607c2bfde7d8399fd0080f
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-22 12:00:30 +08:00
Yakir Yang
c1c93565ff input: touchscreen: fix kernel crash in fb_notifier_callback function
fb_event would only carry the data number in some special notify action,
other actions wouldn't carry an valid data number, and in this case
kernel would crash, logs like:

[    4.129846] Unable to handle kernel paging request at virtual address 200000000000
......
[    4.164618] Hardware name: Rockchip RK3399 Evaluation Board v1 (Chrome OS) (DT)
[    4.184624] PC is at fb_notifier_callback+0x28/0xac
[    4.189497] LR is at notifier_call_chain+0x74/0xb4
[    4.194279] pc : [<ffffffc0005e1468>] lr : [<ffffffc0000b5ba4>] pstate: 20000045
......
[    5.703780] [<ffffffc0005e1468>] fb_notifier_callback+0x28/0xac
[    5.709690] [<ffffffc0000b5ba4>] notifier_call_chain+0x74/0xb4
[    5.715504] [<ffffffc0000b5e70>] __blocking_notifier_call_chain+0x48/0x64
[    5.722280] [<ffffffc0000b5ea0>] blocking_notifier_call_chain+0x14/0x1c
[    5.728885] [<ffffffc00036fd98>] fb_notifier_call_chain+0x20/0x28
[    5.734969] [<ffffffc0003726c0>] register_framebuffer+0x218/0x250
[    5.741054] [<ffffffc0003b7598>] drm_fb_helper_initial_config+0x2f8/0x374
[    5.747832] [<ffffffc0003e056c>] rockchip_drm_fbdev_init+0xa8/0xe8
[    5.754002] [<ffffffc0003dba24>] rockchip_drm_load+0x1e4/0x25c

Change-Id: I3314315a31bbab43489fca85dabc4c6511fc9dee
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-22 12:00:03 +08:00
Elaine Zhang
f40bf059ea UPSTREAM: soc: rockchip: power-domain: support qos save and restore
support qos save and restore when power domain on/off.

Change-Id: I5cecf9755467290bc153eeeb75dfd009e7736820
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
 commit 074c6a422d)
2016-04-22 10:52:17 +08:00
Elaine Zhang
47138e271d UPSTREAM: dt-bindings: modify document of Rockchip power domains
Rockchip Socs contain quality of service (qos) blocks managing priority,
bandwidth, etc of the connection of each domain to the interconnect.
These blocks loose state when their domain gets disabled and therefore
need to be saved when disabling and restored when enabling a power-domain.

These qos blocks also are similar over all currently available Rockchip
SoCs.

Change-Id: I03c80e01ae0fd1a66a67db15f24869047862f13f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
 commit 71daabca34)
2016-04-22 10:52:17 +08:00
Shawn Lin
aa7c7be40e UPSTREAM: soc: rockchip: power-domain: check the existing of regmap
Check return value of syscon_node_to_regmap for
rockchip_pm_domain_probe. If err value is returned, probe
procedure should abort.

Change-Id: I8b6f2a62d383c5cae5b69e030a8a8e2ad9cc18c1
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
 commit 4506697d9f)
2016-04-22 10:52:16 +08:00
Finley Xiao
4600240316 ARM64: dts: rockchip: rk3366: assign parent for gpu and wifi.
Gpu's 480MHz need to select usbphy_480m as parent.
The jitter will be lower, if sclk_wifidsp is supplied by pll_wifi.

Change-Id: I13e5077d55ab80e5224bac36b469e39d556bd347
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2016-04-21 19:56:37 +08:00
Finley Xiao
4a4215ae12 clk: rockchip: rk3366: modify the parent's name of usbphy480m
Change-Id: I6a628a96acba4e73405ffc58fbd9a8f6e4544e4f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2016-04-21 19:54:53 +08:00
Finley Xiao
5aeb54a9be UPSTREAM: clk: Add clk_composite_set_rate_and_parent
When changing the clock-rate, currently a new parent is set first and a
divider adapted thereafter. This may result in the clock-rate overflowing
its target rate for a short time if the new parent has a higher rate than
the old parent.

While this often doesn't produce negative effects, it can affect components
in a voltage-scaling environment, like the GPU on the rk3399 socs, where
the voltage than simply is to low for the temporarily to high clock rate.

For general clock hirarchies this may need more extensive adaptions to
the common clock-framework, but at least for composite clocks having
both parent and rate settings it is easy to create a short-term solution to
make sure the clock-rate does not overflow the target.

Change-Id: Iceb40b24ef13db6947be3d797ea90b3e1055b9df
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org clk/linux.git clk-next
 commit 9e52cec04f)
2016-04-21 15:20:50 +08:00
Heiko Stuebner
296f608d55 UPSTREAM: clk: rockchip: reign in some overly long lines in the rk3399 controller
We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.

Fix the newly added rk3399 clock code to respect that.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org kernel/git/mmind/linux-rockchip.git
v4.7-clk/next commit 995d3fdeb2)

Conflicts:

	drivers/clk/rockchip/clk-rk3399.c
[
zx: this patch is based on the old version by Heiko on the upstream:
commit de4939f7fc
Author: Xing Zheng <zhengxing@rock-chips.com>
Date:   Fri Mar 25 19:33:48 2016 +0800

    clk: rockchip: rk3399: add some aclk/dclk IDs for vop0/vop1
]

Change-Id: I6aeda93a54ab96ab885f9bf04a5f21b07d1c9a89
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-04-21 11:52:24 +08:00
Xubilv
e7bc0d93fe ARM64: dts: rk3399-fb: include mipi_dsi.h for mipi command mode of timing file
Change-Id: I4426ff9f47abfa7de99b79078370740226871f44
Signed-off-by: Xubilv <xbl@rock-chips.com>
2016-04-20 19:01:54 +08:00
Xubilv
764447e140 ARM64: dts: rk3368: include mipi_dsi.h for mipi command mode of timing file
Change-Id: Id80b519c7c45678d6163828f4d500f1fc5742343
Signed-off-by: Xubilv <xbl@rock-chips.com>
2016-04-20 19:00:59 +08:00
Xubilv
2562ee6fdb ARM64: dts: rk3366: include mipi_dsi.h for mipi command mode of timing file
Change-Id: Ib1e43d4df5735c2364138423d9622fd906ff5349
Signed-off-by: Xubilv <xbl@rock-chips.com>
2016-04-20 19:00:39 +08:00
Yakir Yang
48bb3848c6 ARM64: configs: rockchip_defconfig: enable DRM RGA support
Change-Id: I8516f9ad6c4c539839135449b36d74649443adf9
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-20 18:59:53 +08:00
Yakir Yang
3b8ee0bc65 ARM64: configs: rockchip_cros_defconfig: enable DRM RGA driver support
Change-Id: I4da9799d9e7fc824893b9b19b0e62cc03156ab54
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-20 18:59:12 +08:00
Yakir Yang
a5cecab19b ARM64: dts: rk3399: add RGA device node
Change-Id: Ia8bc692fb7395b8dc1bff339aa18282ae91b2024
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-20 18:57:00 +08:00
Yakir Yang
2e3839fcf7 dt-bindings: add document for Rockchip RGA module
RGA is a separate 2D raster graphic acceleration unit.

Change-Id: I510a4799e6c69afe01b2f2adfd6be84e322ff9f2
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-20 18:53:03 +08:00
Yakir Yang
3e2bb4ee5b drm/rockchip: add RGA driver support
Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness.

Change-Id: I9be8d683ea04802affb973b8b1ada646afe411d7
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-20 18:52:25 +08:00
Yakir Yang
bb88c2a1c5 drm/rockchip: add a common subdrv interfaces
Introduce a common subdrv register/unregister interfaces, help
sub-driver to hook the drm open/close event.

Change-Id: I42a563504dd8d8e26f34946067e6e60f1ee88379
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2016-04-20 18:47:59 +08:00
Huang Jiachai
780c7a3ec1 ARM64: dts: rk3399-fb: enable vop iommu
Change-Id: I42fd20b89205d53f539ab37ce65347d3c7b4ce9e
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
2016-04-20 15:59:44 +08:00
Huang Jiachai
5194e73a9c video: rockchip: vop: 3399: update for AFBDC
1.gpu afbc default in yuv color;
2.mb width and hight is equal to xvir and yvir.

Change-Id: I905d90c8a75c0b5136ff883fbcf7128ca954e425
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
2016-04-20 15:59:28 +08:00
Huang Jiachai
3edabc137d video: rockchip: fb: add vopid for screen switch uevent
Change-Id: Ib51af94397758a2118b6a41e1c736ac454e12b85
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
2016-04-19 21:01:53 +08:00
Zain Wang
e95935fec3 regulator: mp8865: update mp8865 driver
set slew rate 1.6mV/uS, set switch_frequency 1.1MHz,
support enable_time 100us and add regmap cache.

Change-Id: I8fb2147b5a574ab96f5e3601cb5ac24412676045
Signed-off-by: Zain Wang <wzz@rock-chips.com>
2016-04-19 11:53:04 +08:00
Jianqun Xu
41cbb9424f ARM64: dts: rk3399: add dts files for evb rev2
Change-Id: I40abefbae2377f4f86a54b5b752b831acd592d10
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2016-04-19 10:31:36 +08:00
Jianqun Xu
96576852a7 ARM64: dts: rk3399: rename dts files
Rename the rk3399 dts files:
    rk3399-monkey.dts -> rk3399-evb1-android.dts
    rk3399-chrome.dts -> rk3399-evb1-cros.dts
    rk3399-tb.dtsi -> rk3399-evb.dtsi

Change-Id: Ie1f61d63b8fefc263a64d713d70947ceee8472c5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2016-04-19 10:31:06 +08:00
Xing Zheng
88a43f2f1a clk: rockchip: rk3399: Export isp clock IDs
Change-Id: I6f8a2192d6f69b23ba4fa3ad6e973aba9120399a
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-04-19 10:29:13 +08:00
Xing Zheng
56291663d1 clk: rockchip: rk3399: Add and export SCLK_RGA_CORE clock id
Change-Id: Ia64289f565e7b4570c6b55810bda5d4711a7381a
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-04-19 10:27:18 +08:00
Wu Liang feng
06ed11d415 usb: gadget: composite: don't queue OS desc request if req length is invalid
In OS descriptors handling, if ctrl->bRequestType is USB_RECIP_DEVICE
and w_index != 0x4 or (w_value >> 8) is true, it will not reset
req->length, but use the default value(-EOPNOTSUPP), and queue an
OS desc request with an invalid req->length. It always happens
on the platforms which use os_desc(for example: rk3366,rk3399),
and cause kernel panic as follows(use dwc3 driver):

Unable to handle kernel paging request at virtual address ffffffc0f7e00000
Internal error: Oops: 96000146 [#1] PREEMPT SMP
PC is at __dma_clean_range+0x18/0x30
LR is at __swiotlb_map_page+0x50/0x64
Call trace:
 [<ffffffc0000930f8>] __dma_clean_range+0x18/0x30
 [<ffffffc00062214c>] usb_gadget_map_request+0x134/0x1b0
 [<ffffffc0005c289c>] __dwc3_ep0_do_control_data+0x110/0x14c
 [<ffffffc0005c2d38>] __dwc3_gadget_ep0_queue+0x198/0x1b8
 [<ffffffc0005c2e18>] dwc3_gadget_ep0_queue+0xc0/0xe8
 [<ffffffc00061cfec>] composite_ep0_queue.constprop.14+0x34/0x98
 [<ffffffc00061dfb0>] composite_setup+0xf60/0x100c
 [<ffffffc0006204dc>] android_setup+0xd8/0x138
 [<ffffffc0005c29a4>] dwc3_ep0_delegate_req+0x34/0x50
 [<ffffffc0005c3534>] dwc3_ep0_interrupt+0x5dc/0xb58
 [<ffffffc0005c0c3c>] dwc3_thread_interrupt+0x15c/0xa24

With this patch, the gadget driver will not queue a request and
return immediately if req->length is invalid. And the usb controller
driver can handle the unsupport request correctly.

Change-Id: I60270d7c12fa190a99cd1079880a2f7167e7af27
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
2016-04-19 09:14:38 +08:00
Xubilv
5e393383bc video: rockchip: mipi: rk3399: add power domain control
Change-Id: I61c2ad075417a716b1ba7c73baf4fd5889b402e9
Signed-off-by: Xubilv <xbl@rock-chips.com>
2016-04-18 20:50:08 +08:00
Mark Yao
eab94f6acf video: rockchip: vop: 3399: fix afbdc abnormal
The vop mask write need use u64 value.

Change-Id: I020fdf4e7115b2763dd732be6542589f61190f4a
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2016-04-18 18:29:35 +08:00