Without MMC_CAP_ERASE support, we fail to mount partition
with "discard" option since mmc_queue_setup_discard is limited
for checking mmc_can_erase. Without doing mmc_queue_setup_discard,
blk_queue_discard fails to test QUEUE_FLAG_DISCARD flag, so we get
the following log from f2fs(actually similar to other file system):
mounting with "discard" option, but the device does not support discard
Change-Id: Iee781795c9c61153644f0dd5b00dfc2cca6cc721
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
As the TRM says, add the tsadc_q_sel to control the temperature-code
sequence since the rk3228/rk3399 need set this bit (1024 - tsadc_q)
as output.
Fixes: commit
b0d7033 "thermal: rockchip: Support the RK3399 SoCs in thermal driver"
7b02a5e "thermal: rockchip: Support the RK3228 SoCs in thermal driver"
Reported-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
(cherry picked from git.kernel.org evalenti/linux-soc-thermal fixes
commit 7ea38c6c36)
Change-Id: I9d39b947e197393688ed58bf079e519e7d5a6d9e
This patch renames to be more adapter compatibles since more and more
SoCs are supported in thermal driver.
Reported-by: Huang,Tao <huangtao@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
(cherry picked from git.kernel.org evalenti/linux-soc-thermal fixes
commit 952418a34f)
Change-Id: Ia053d6877a16b36e357bd9b427b323703e5a514b
If phy_pm_runtime_get_sync failed but we already
enable regulator, current code return directly without
doing regulator_disable. This patch fix this problem
and cleanup err handle of phy_power_on to be more readable.
Fixes: 3be88125d8 ("phy: core: Support regulator ...")
Cc: <stable@vger.kernel.org> # v3.18+
Cc: Roger Quadros <rogerq@ti.com>
Cc: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
(cherry picked from commit b82fcabe21)
Change-Id: I1cb5327d624d88a97096eccaa94924b851dcce27
fixed the WARNING: invalid free of devm_ allocated data
Change-Id: I54514cf53a8a0d1f885fd0a17e7f6db7af1d10f9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
For gadget driver, usb_ep_caps is a new structrue in usb_ep, and its
attribute will be check in usb_ep_autoconfig method, so we need to do
some initialization work at ep creating.
Meanwhile, the process of android gadget driver have been changed,
correspondingly, udc_start and udc_stop are invoked differently from
before, so dwc_otg_gadget_stop method need to refactor and ajust
the new process.
Change-Id: Id1e20d4c265e0d382b0f36f6e729681f9c94c947
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
Access the PHY via registers provided by GRF (general register
files) module.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
(cherry picked from git.kernel.org kishon/linux-phy next
commit 9743f1c935995a55ddd926943ee7b3cfb4718208)
Change-Id: Ia24ccd041392e64efd28868ffccc8da4419bd29f
This patch adds a binding that describes the Rockchip eMMC PHYs
found on Rockchip SoCs eMMC interface.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
(cherry picked from git.kernel.org kishon/linux-phy next
commit c9a1ddcac5b95a9dbf3d3f71d3be8b157239cce5)
Change-Id: I6913babddbc70c1ad3ea2234d8afac79190852a4
enable PM_ADVANCED_DEBUG by default.
use pd debug get pd tree like this:
cat d/pm_genpd/pm_genpd_summary
Change-Id: I1ca27a7619cc0655c2256918d7b6530b6a637bcf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The USB phys on Rockchip SoCs contain their own internal PLLs to create
the 480MHz needed. Additionally this PLL output is also fed back into the
core clock-controller as possible source for clocks like the GPU or others.
Until now this was modelled incorrectly with a "virtual" factor clock in
the clock controller. The one big caveat is that if we turn off the usb phy
via the siddq signal, all analog components get turned off, including the
PLLs. It is therefore possible that a source clock gets disabled without
the clock driver ever knowing, possibly making the system hang.
Therefore register the phy-plls as real clocks that the clock driver can
then reference again normally, making the clock hirarchy finally reflect
the actual hardware.
The phy-ops get converted to simply turning that new clock on and off
which in turn controls the siddq signal of the phy.
Through this the driver gains handling for platform-specific data, to
handle the phy->clock name association.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
(cherry picked from commit b74fe7c761)
Change-Id: Ie05464a9523af86b602d4801cb9b842f65d08670
We need custom handling for these two socs in the driver shortly,
so add the necessary compatible values to binding and driver.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
(cherry picked from commit c2bfc3b888)
Change-Id: I63cf61e12b1f3bb56856accc38949c6cd8c0ce8e
This unclutters the loop in probe a lot and makes current (and future)
error handling easier to read.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
(cherry picked from commit 97dd910109)
Change-Id: I5c2ccfbd42e52b77649f01bca2a86767f27fe32f
This introduces a common struct that holds data belonging to
the umbrella device that contains all the phys and that we
want to use later.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
(cherry picked from commit 5fdbb97dec)
Change-Id: I48dd87b0b39739e0c75d0613e881b2b57e8cb6f2
Currently the phy driver only gets the optional clock reference but
never puts it again, neither during error handling nor on remove.
Fix that by moving the clk_put to a devm-action that gets called at
the right time when all other devm actions are done.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
(cherry picked from commit 75d390fecf)
Change-Id: I976d5a49448febdb7da5b5c35455c708bfc83899
add pd parameters in the dtsi.
support pd for rk3366.
Change-Id: Id8a7c7b84038e4987aea8cb0e9846fbe187af0e9
Signed-off-by: Xiao Feng <xf@rock-chips.com>
According to a description from TRM, add all the power domains.
Change-Id: I65046318da4592b76bfd5ab7c0294e2c5d66d20a
Signed-off-by: Xiao Feng <xf@rock-chips.com>
Modify binding documentation for the power domains
found on Rockchip RK3366 SoCs.
Change-Id: Ib9cd07971303b1205f501a06430811e877870212
Signed-off-by: Xiao Feng <xf@rock-chips.com>
Modified some internal interfaces to support kernel-4.4
Change-Id: I1a87b75f5429874d879437b21cbf85eba4473ee0
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Because the RK3399 CRU TRM is updating, so we need to maintain a
consistent naming clock IDs.
Change-Id: I1724827f05f4f44b197c14a5d81fec5afc1202b5
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported RK3366 SoCs.
Change-Id: Idabfe85f269b8f15f85471daa50c3ef988b21297
Signed-off-by: Xiao Feng <xf@rock-chips.com>
Rockchip SoC such RK3366 has VOP-LITE controller. This patch
supports VOP-LITE driver base on Rockchip SoC Chip.
Change-Id: I64ea2307609530f7dc0dbe6b1c9b3059d1cf821d
Signed-off-by: Wenlong Zhuang <daisen.zhuang@rock-chips.com>
Make it possible to specify the supply of a regulator, through the
tp-supply property in dt.
Change-Id: If741bb48280a339fc37e9f53d566fbbb444c31e8
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
enable/disable master clock when codec is active or not.
Change-Id: Ia876abde08138c4f23ed5a1a684f6637c42d5e34
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
this patch add default values for registers according description from TRM.
Change-Id: I683b30483b9c1db08a202983f7055092db4cad2e
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
because i2s have no child devices so address-cells and
size-cells properties are not required. remove these from dts.
Change-Id: Iaaeec7907fd565279a01c0051353c7170af0812c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
To model the muxes downstream of fractional dividers we introduced the
child property, allowing to describe a direct child clock.
The first implementation seems to cause section warnings, as the core
clock-tree is marked as initdata while the data pointed to from the
child element is not.
While there may be some way to also set that missing property in the
inline notation I didn't find it, so to actually fix the issue for now
move the sub-definitions into separate declarations that can have
their own __initdata properties.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
(cherry picked from commit 5b73840375)
Change-Id: I22c03dea33af24ba5743170325f318432cfd766f
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported RK3036 SoCs.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
(cherry picked from commit b0158bb27c)
Change-Id: Ief8f77ec66c8b281d52d1e19dcd50d2f7b663045
The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288
SoCs only feed those clocks, allow those clocks to change their parents
all the way up the hierarchy.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
(cherry picked from commit 84a8c54166)
Change-Id: Id362013ba195fdb88e4cdbaed2468deaafc04e64
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported Rockchip SoCs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
(cherry picked from commit 6674642089)
Change-Id: I243f17bf622b278ec365755f7fb4da90843107d7
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature"
that requires the downstream mux to actually point to the fractional
divider and the fractional divider gate to be enabled, for it to really
accept changes to the divider ratio.
The downstream muxes themselfs are not generic enough to include them
directly into the fractional divider, as they have varying sources of
parent clocks including not only clocks related to the fractional
dividers but other clocks as well.
To solve this, allow our clock branches to specify direct child clock-
branches in the new child property, let the fractional divider register
its downstream mux through this and add a clock notifier that temporarily
switches the mux setting when it notices rate changes to the fractional
divider.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
(cherry picked from commit 8ca1ca8f60)
Change-Id: Ic538fcf248f1e8a7ac87a45788167855155ca54a
