When changing the clock-rate, currently a new parent is set first and a
divider adapted thereafter. This may result in the clock-rate overflowing
its target rate for a short time if the new parent has a higher rate than
the old parent.
While this often doesn't produce negative effects, it can affect components
in a voltage-scaling environment, like the GPU on the rk3399 socs, where
the voltage than simply is to low for the temporarily to high clock rate.
For general clock hirarchies this may need more extensive adaptions to
the common clock-framework, but at least for composite clocks having
both parent and rate settings it is easy to create a short-term solution to
make sure the clock-rate does not overflow the target.
Change-Id: Iceb40b24ef13db6947be3d797ea90b3e1055b9df
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org clk/linux.git clk-next
commit 9e52cec04f)
We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.
Fix the newly added rk3399 clock code to respect that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org kernel/git/mmind/linux-rockchip.git
v4.7-clk/next commit 995d3fdeb2)
Conflicts:
drivers/clk/rockchip/clk-rk3399.c
[
zx: this patch is based on the old version by Heiko on the upstream:
commit de4939f7fc
Author: Xing Zheng <zhengxing@rock-chips.com>
Date: Fri Mar 25 19:33:48 2016 +0800
clk: rockchip: rk3399: add some aclk/dclk IDs for vop0/vop1
]
Change-Id: I6aeda93a54ab96ab885f9bf04a5f21b07d1c9a89
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
RGA is a separate 2D raster graphic acceleration unit.
Change-Id: I510a4799e6c69afe01b2f2adfd6be84e322ff9f2
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness.
Change-Id: I9be8d683ea04802affb973b8b1ada646afe411d7
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Introduce a common subdrv register/unregister interfaces, help
sub-driver to hook the drm open/close event.
Change-Id: I42a563504dd8d8e26f34946067e6e60f1ee88379
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
1.gpu afbc default in yuv color;
2.mb width and hight is equal to xvir and yvir.
Change-Id: I905d90c8a75c0b5136ff883fbcf7128ca954e425
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
set slew rate 1.6mV/uS, set switch_frequency 1.1MHz,
support enable_time 100us and add regmap cache.
Change-Id: I8fb2147b5a574ab96f5e3601cb5ac24412676045
Signed-off-by: Zain Wang <wzz@rock-chips.com>
In OS descriptors handling, if ctrl->bRequestType is USB_RECIP_DEVICE
and w_index != 0x4 or (w_value >> 8) is true, it will not reset
req->length, but use the default value(-EOPNOTSUPP), and queue an
OS desc request with an invalid req->length. It always happens
on the platforms which use os_desc(for example: rk3366,rk3399),
and cause kernel panic as follows(use dwc3 driver):
Unable to handle kernel paging request at virtual address ffffffc0f7e00000
Internal error: Oops: 96000146 [#1] PREEMPT SMP
PC is at __dma_clean_range+0x18/0x30
LR is at __swiotlb_map_page+0x50/0x64
Call trace:
[<ffffffc0000930f8>] __dma_clean_range+0x18/0x30
[<ffffffc00062214c>] usb_gadget_map_request+0x134/0x1b0
[<ffffffc0005c289c>] __dwc3_ep0_do_control_data+0x110/0x14c
[<ffffffc0005c2d38>] __dwc3_gadget_ep0_queue+0x198/0x1b8
[<ffffffc0005c2e18>] dwc3_gadget_ep0_queue+0xc0/0xe8
[<ffffffc00061cfec>] composite_ep0_queue.constprop.14+0x34/0x98
[<ffffffc00061dfb0>] composite_setup+0xf60/0x100c
[<ffffffc0006204dc>] android_setup+0xd8/0x138
[<ffffffc0005c29a4>] dwc3_ep0_delegate_req+0x34/0x50
[<ffffffc0005c3534>] dwc3_ep0_interrupt+0x5dc/0xb58
[<ffffffc0005c0c3c>] dwc3_thread_interrupt+0x15c/0xa24
With this patch, the gadget driver will not queue a request and
return immediately if req->length is invalid. And the usb controller
driver can handle the unsupport request correctly.
Change-Id: I60270d7c12fa190a99cd1079880a2f7167e7af27
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This patch fixes following compile error in dwc3 if select
CONFIG_USB_DWC3_HOST.
drivers/usb/dwc3/core.c:874: undefined reference to `dwc3_gadget_restart'
drivers/usb/dwc3/core.c:880: undefined reference to `dwc3_gadget_restart'
which was caused by commit
commit 9607f47dfe
usb: dwc3: add functions to set force mode
Change-Id: Id0abaf89fba006609dbf2e7a771149453465b371
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This adds thermal zone node to rk3399 dtsi, rk3399 thermal data is
including the cpu and gpu sensor zone node.
At the moment, remove the rk3368 thermal data from rk399 dtsi.
The thermal zone node is the node containing all the required info
for describing a thermal zone, including its cooling device bindings. The
thermal zone node must contain, apart from its own properties, one sub-node
containing trip nodes and one sub-node containing all the zone cooling maps
The following is the parameter is introduced:
* polling-delay:
The maximum number of milliseconds to wait between polls
* polling-delay-passive:
The maximum number of milliseconds to wait between polls when performing
passive cooling.
* trips:
A sub-node which is a container of only trip point nodes required to describe
the thermal zone.
* cooling-maps:
A sub-node which is a container of only cooling device map nodes, used to
describe the relation between trips and cooling devices.
* cooling-device:
A phandle of a cooling device with its specifier, referring to which cooling
device is used in this cooling specifier binding. In the cooling specifier,
the first cell is the minimum cooling state and the second cell is the maximum
cooling state used in this map.
Change-Id: I76c5829fdc120cd5da078e2937abeee720ee379c
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Whenever the current temperature is updated, the trip points immediately
below and above the current temperature are found. A sensor driver
callback `set_trips' is then called with the temperatures.
Lastly, The sensor will trigger the hardware high temperature interrupts
to increase the sampleing rate and throttle frequency to limit the temperature
rising When performing passive cooling.
Change-Id: I43d37a8431240cb7b62da7bff83464aba3c8983e
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This adds support for hardware-tracked trip points to the device tree
thermal sensor framework.
The framework supports an arbitrary number of trip points. Whenever
the current temperature is updated, the trip points immediately
below and above the current temperature are found. A sensor driver
callback `set_trips' is then called with the temperatures.
If there is no trip point above or below the current temperature,
the passed trip temperature will be LONG_MAX or LONG_MIN respectively.
In this callback, the driver should program the hardware such that
it is notified when either of these trip points are triggered.
When a trip point is triggered, the driver should call
`thermal_zone_device_update' for the respective thermal zone. This
will cause the trip points to be updated again.
If the `set_trips' callback is not implemented (is NULL), the framework
behaves as before.
CQ-DEPEND=CL:*210768
BUG=chrome-os-partner:30834
TEST=None
Change-Id: I33226d2b80f3e71a0c3ca3fbc5718db4e461268f
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Signed-off-by: Wei Ni <wni@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/212425
Reviewed-by: Olof Johansson <olofj@chromium.org>
Commit-Queue: Olof Johansson <olofj@chromium.org>
Tested-by: Olof Johansson <olofj@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/210454
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/267514
Tested-by: David Riley <davidriley@chromium.org>
Reviewed-by: David Riley <davidriley@chromium.org>
Commit-Queue: David Riley <davidriley@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(cherry-picked from https://chromium.googlesource.com/chromiumos/
third_party/kernel/+/v3.18 commit 397befabb2a52fc16586509a970f8c98268b8040)
We need the cpu throttle and IPA function for rockchip.
Also enable the writable trips function.
Let's enable the needed config for thermal.
Change-Id: Ibd43aa4ef3cc5e0a325e376d753cffc8bcdb8c02
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The endpoint order would decide the priority of connector devices,
the higher the priority ranking.
For now eDP can't light up with VOP Lit, so we need to cut down
the priority that eDP in VOP Lit, and raise up the priority that
MIPI in VOP Lit.
Change-Id: Ide4e321f03cf7ad5080c6db7f9230962963a3eb8
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This is a hack way to let VOP Big to select eDP device when VOP
Big and Lit all enabled.
Change-Id: Ia2bc91ff903bbc7d00deed57aab315328ce54378
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Fix a typo making the clk_cifout access a
wrong clk tree to handle its mux and div.
Change-Id: Ief20e684eadd10b75cf36120df16f13c7581d303
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Panel brightness is controller by EC, the AP just enable/disable the
backlight power through GPIO1_C1.
Change-Id: I46e1f3b5098159cb07f86ba203ef8cfa102dd385
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The RK3399 EVB board is using the LG LP097QX1-SPA1
9.7" 2048x1536 eDP panel.
Change-Id: I837b0a569605591756918b12f56dbaa0b1f3f8d4
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Until we get PWM regulator solid, let's hack it out and just keep
whatever the firmware set for us.
Note that when the kernel boots it appears that it does some reparenting
of clocks and the PWM frequency actually changes. ...but the voltage
seems OK ish.
Change-Id: I3be6ea4460f685e4a75a0f7f31f767f09b908442
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254650
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(Fixes the typo)
the hw default of the dvs2 is pull up which is not correct.
set the dvs2 gpio pull down.
Change-Id: I0d296cecc422456cb72630d5ce64a5c7e5dad283
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Until we get all the magic PWM regulator stuff solved with Boris's
wonderful upstream patches, let's just hack the PWM clock to be critical
so it never turns off. Nuff said.
Change-Id: I99660b0b188413eb08030a3ae87c045c338b30db
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254649
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(Fixes the pclk_rkpwm_pmu into pmucru_critical_clock)
We should make sure the config generate from the savedefconfig.
Okay, anyway cleanup the config with run 'make ARCH=arm64 savedefconfig'.
Change-Id: Ia094322870d378183760e32b7177971342e48439
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The eDP panel of Kevin board only have a AP GPIO to control
the backlight power, so we need to enable the GPIO backlight
type for it.
Change-Id: I939e1c658b56ee5d889af820985f9ffd46f50485
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD
panel connected using eDP interfaces.
Change-Id: Ib5164763d18c5cffcc83b38715f559a4a0c02638
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel
connected using eDP interfaces.
Change-Id: I3c2208fc45b53b0fab328fcb9ba204f610a9f9f6
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
AFAIK, the hardware designed that TSHUT should be set the active high.
Since rk3399 evb designed the over-temperature protection pin is
connected to PMIC that active high vaild.
Also, as gru/kevin designed the over-temperature protection pin is
connected to EC control that active high to prevent leakage.
Change-Id: Ib7b15d115d2ea4e474918fc416dde273b040e740
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The hardware IC designed that VOP must output the RGB10 video format to
eDP contoller, and if eDP panel only support RGB8, then eDP contoller
should cut down the video data, not via VOP contoller, that's why we need
to hardcode the VOP output mode to RGA10 here.
Change-Id: I733eae8a5dda51c0288d8627ceffb39a2f804e62
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Rockchip VOP couldn't output YUV video format for eDP controller, so
when driver detect connector support YUV video format, we could hack
it down to RGB888.
Change-Id: Ia876bb49e772f85bef201af2b62dd558d6b99257
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
It's helpful to expand the mode_valid callback to platform driver,
so they could valid the display mode or informations.
Change-Id: Icfd7593bd10c93fc9045acf04a8d0ed6336ffb85
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
