We want add display support on loader, share the same timing
with kernel side, but the timing is hide into kernel code,
can't be share, avoid config twice display timing, add device-tree
display timing support would be good idea.
With this patch, loader and kernel can share same timing from
device node.
Cc: Thierry Reding <thierry.reding@gmail.com>
Change-Id: I6c1ee6ad0194e242035e2f11589d86fdb363b80a
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9238727)
Current dw-hdmi is supporting sound via AHB bus, but it has
I2S audio feature too. This patch adds I2S audio support to dw-hdmi.
This HDMI I2S is supported by using ALSA SoC common HDMI encoder
driver.
Change-Id: I32e95f66838883ac44a45f95c55583184a0a1b46
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am form https://patchwork.kernel.org/patch/9196453/)
Commit b360d3748e ("ASoC: hdmi-codec: callback function will be called
with private data") have introduced an external parameter in struct
hdmi_codec_ops, so need to fix the old interfaces.
Change-Id: Iaebd49ba7eb7fc0d857ff8aa8f9af39ea4678143
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
There are some rates that would be ranged for better clock jitter at
Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz.
But due to the clock is aglined to KHz in struct drm_display_mode,
this would bring some inaccurate error if we still run the compute_n
math, so let's just code an const table for it until we can actually
get the right clock rate.
Change-Id: Ief14b7c9bffa95ff3b173925f3e1bd795625320d
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/316280
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
The original math would bring some inaccurate to N/CTS that would
caused those magic number won't fit the HDMI 1.4 Spec request:
128 * SampleRate = Tmds * N / CTS;
So this time we try to improved to math of N that would find the
minimal inaccurate with the HDMI 1.4 Spec.
Change-Id: Ied3cde3c352d955ae6f15d5e7fb172e92316c2a5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/315424
Reviewed-by: Douglas Anderson <dianders@chromium.org>
We allow some amount of slop in dw_hdmi_rockchip_mode_valid(). That's
a good thing since allowing a little bit of slop lets us support a
bunch of extra resolutions.
Originally, we also made a change to the VOP code to add the concept
of slop in there. That was reasonable, but there was a problem: it
would tend to request clock rates that weren't _exactly_ clock rates
that we thought about. It's possible that the common clock framework
would map these to PLL rates that we haven't thought about and we
haven't tested for jitter.
Instead of changing VOP, we should probably adjust the clock ourselves
in the mode_fixup function. That way we'll request the exact clock we
tested and we'll know how the common clock framework will map it.
Change-Id: I56c2b046f76d554aab5eaed7a6b171ea074d6a62
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/284376
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Add a check just to make sure that someone doesn't try to give us a
pixel clock that is > 2GHz. If they did that, some of our math might
overflow, so it's good to make sure we don't do it.
Change-Id: I451602f0d771bb16b399b43e376e1054b7ee060f
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/284642
Reviewed-by: Alexandru Stan <amstan@chromium.org>
This cleanup will allow the following patch to implement slop easier.
25175000-40000000 and a few other ranges use the same settings.
And the rest of the driver already snaps to the next highest
frequency when it gets the settings. So this patch removes
a lot of the duplicates. It should be a noop change.
And frequencies within 0.1% should be close enough, let's redo
rockchip hdmi to allow slop.
Change-Id: Ic4865b2825de9b6c3b3e8d029066a8964e8ede6b
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reference the power domain incase dw-mipi power down when
in use.
Change-Id: I54a0f418f20299a744f87c1337f06ff3341dfac5
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
We want to display a buffer allocated by other driver, need import
the buffer to gem.
Change-Id: Ifd5fef3fbf2b4daea6d624ed2a250c2fe626309d
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
For RK3399's GRF module, if we want to operate the graphic related grf
registers, we need to enable the pclk_vio_grf which supply power for VIO
GRF IOs, so it's better to introduce an optional grf clock in driver.
Change-Id: I8f43e5c46c8559d6b6fe96a12cd026319b1d84e5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9223317/)
For RK3399 HDMI, there is an external clock need for HDMI PHY,
and it should keep the same clock rate with VOP DCLK.
VPLL have supported the clock for HDMI PHY, but there is no
clock divider bewteen VPLL and HDMI PHY. So we need to set the
VPLL rate manually in HDMI driver.
Change-Id: I73abc382ff43bfa93d150c3449693f207029549f
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9223327/)
RK3399 and RK3288 shared the same HDMI IP controller, only some light
difference with GRF configure.
Change-Id: Ic404ff3df6004a87b709f00552d91eb546c78450
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9223315/)
The previous tables for mpll_cfg and curr_ctrl were created using the
20-pages of example settings provided by the PHY vendor. Those
example settings weren't particularly dense, so there were places
where we were guessing what the settings would be for 10-bit and
12-bit (not that we use those anyway). It was also always a lot of
extra work every time we wanted to add a new clock rate since we had
to cross-reference several tables.
In <http://crosreview.com/285855> I've gone through the work to figure
out how to generate this table automatically. Let's now use the
automatically generated table and then we'll never need to look at it
again.
We only support 8-bit mode right now and only support a small number
of clock rates and and I've verified that the only 8-bit rate that was
affected was 148.5. That mode appears to have been wrong in the old
table.
Change-Id: I42b260300880f2bab6732c5ee3b11bc78e87500c
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
(am from https://patchwork.kernel.org/patch/9223325)
Dut to the high HDMI signal voltage driver, Mickey have meet
a serious RF/EMI problem, so we decided to reduce HDMI signal
voltage to a proper value.
The default params for phy is cklvl = 20 & txlvl = 13 (RF/EMI failed)
ck: lvl = 13, term=100, vlo = 2.71, vhi=3.14, vswing = 0.43
tx: lvl = 20, term=100, vlo = 2.81, vhi=3.16, vswing = 0.35
1. We decided to reduce voltage value to lower, but VSwing still
keep high, RF/EMI have been improved but still failed.
ck: lvl = 6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50
tx: lvl = 6, term=100, vlo = 2.61, vhi=3.11, vswing = 0.50
2. We try to keep voltage value and vswing both lower, then RF/EMI
test all passed ;)
ck: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40
tx: lvl = 11, term= 66, vlo = 2.68, vhi=3.09, vswing = 0.40
When we back to run HDMI different test and single-end test, we see
different test passed, but signle-end test failed. The oscilloscope
show that simgle-end clock's VL value is 1.78v (which remind LowLimit
should not lower then 2.6v).
3. That's to say there are some different between PHY document and
measure value. And according to experiment 2 results, we need to
higher clock voltage and lower data voltage, then we can keep RF/EMI
satisfied and single-end & differen test passed.
ck: lvl = 9, term=100, vlo = 2.65, vhi=3.12, vswing = 0.47
tx: lvl = 16, term=100, vlo = 2.75, vhi=3.15, vswing = 0.39
Change-Id: I766df9ad519ddddb9be76f95fbbdb36c5a2d6e51
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
(am from https://patchwork.kernel.org/patch/9223303/)
Jitter was improved by lowering the MPLL bandwidth to account for high
frequency noise in the rk3288 PLL. In each case MPLL bandwidth was
lowered only enough to get us a comfortable margin. We believe that
lowering the bandwidth like this is safe given sufficient testing.
Change-Id: Ife266747f0e6ed46f914f4868362fefc481440f9
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9223301/)
Set unused plane with top zpos will cause a alpha problem.
if there are two planes use same zpos, hardware will do twice
alpha compute, that would cause display abnormal.
Change-Id: I3b5d15c5239412c670ad377edbcc66d7f6c59341
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Some vop can't support 10bit mode, if connector needs 10bit output,
force to use 8bit rgb888 mode, because the hardware would do the
format convert.
Change-Id: I8cdfbab12dd0ad63d36f3c52a4c7786a2bdbe6a1
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
This adds support for Rockchip soc lvds found on rk3288
Change-Id: Iaab32c8c02fb17bf55db97a7952a346ce45c7d09
Signed-off-by: Mark Yao <yzq@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Fill atomic needed funcs with default atomic helper library.
Rockchip use dw_hdmi, and drm/rockchip will covert to atomic api,
we need dw_hdmi support atomic funcs.
Now another drm driver use dw_hdmi is imx, not yet atomic, so
check DRIVER_ATOMIC at runtime to spilt atomic and not atomic.
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Change-Id: I519527efaf88b1e5c1b30db1fd23e59d45b88d50
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(cherry pick from 2c5b2cccdb)
A single blank line is enough to separate Kconfig entries.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Change-Id: I325951cc36a4429a8313b61e3f3a44aa24e49958
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(cherry pick from dae91e4d1c)
For consistency with other drivers, use dashes instead of underscores in
filenames.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Change-Id: Ie872685143935c365b40c3aaf2a104879478ea66
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(cherry pick from 248a86fc30)
LSK 16.06 v4.4-android
* tag 'lsk-v4.4-16.06-android': (447 commits)
Linux 4.4.14
netfilter: x_tables: introduce and use xt_copy_counters_from_user
netfilter: x_tables: do compat validation via translate_table
netfilter: x_tables: xt_compat_match_from_user doesn't need a retval
netfilter: ip6_tables: simplify translate_compat_table args
netfilter: ip_tables: simplify translate_compat_table args
netfilter: arp_tables: simplify translate_compat_table args
netfilter: x_tables: don't reject valid target size on some architectures
netfilter: x_tables: validate all offsets and sizes in a rule
netfilter: x_tables: check for bogus target offset
netfilter: x_tables: check standard target size too
netfilter: x_tables: add compat version of xt_check_entry_offsets
netfilter: x_tables: assert minimum target size
netfilter: x_tables: kill check_entry helper
netfilter: x_tables: add and use xt_check_entry_offsets
netfilter: x_tables: validate targets of jumps
netfilter: x_tables: don't move to non-existent next rule
drm/core: Do not preserve framebuffer on rmfb, v4.
crypto: qat - fix adf_ctl_drv.c:undefined reference to adf_init_pf_wq
netfilter: x_tables: fix unconditional helper
...
Otherwise, clk_gpu won't be disabled actually in the runtime.
Change-Id: If1e32061cbffc1564a5cf95fbf01aa91c827550d
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
Return -EINVAL would cause mipi dsi bad behavior, probe defer
to ensure mipi find the correct mode,
Change-Id: I0bb8e97dd6bd19f66052b4e985e95d8d82faf29b
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
HardWare limited, the bottom layer not support per-pixel alpha,
Change-Id: I174da1d3d3cfff8d0b6cd6dfab4873438895e56d
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Hardware limited, we should keep all unused layer same
with the same zpos, otherwise, would get display abnormal.
Change-Id: I417a6a14731148a89f0372cc028e43a94b56e4d3
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
That is wrong use old crtc mode on atomic check.
Change-Id: Ie37bd842f8bafca04303d641269a84a6016457f4
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
All rockchip drm modules are module_init, so the probe sequence
is judged by compile sequence.
We want the rockchip drm core probe on the last one, so if components
call probe defer on bind, would use rockchip drm core to do probe defer.
Change-Id: Ibda12998545a93327bdf35bc1b8386034189ba6a
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
The AUO B101EW05 panel is a 10.1" 1280(RGB)x800 WXGA TFT-LCD panel,
connected using LVDS interfaces
Change-Id: Ic67fe5793a975b585cecfb8da02e81cd9fa6346f
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Chunghwa CLAA070WP03 is 7” color TFT-LCD module composed of LCD panel,
LVDS driver ICs, control circuit and backlight. This module supports
800x1280 mode.
Change-Id: I6a6339ad25664e2e47fc0e0de5c079db3494bd25
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
32 pins eDP interface. This module supports 1536x2048 mode.
Change-Id: Ib42185ffce772160133a3edf3c3cf61bff4b85c5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201799/)
When the input color format is YUV, we need to do some external scale
for CBCR. Like,
* In YUV420 data format:
cbcr_xscale = dst_w / src_w * 2;
cbcr_yscale = dst_h / src_h * 2;
* In YUV422 data format:
cbcr_xscale = dst_w / src_w * 2;
cbcr_yscale = dst_h / src_h;
* In YUV444 data format
cbcr_xscale = dst_w / src_w;
cbcr_yscale = dst_h / src_h;
Change-Id: I73e0423d3662bd340b5d155996f13d31c22dcc29
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9157353/)
The WIN0 of RK3036 VOP could support YUV data format, but driver
forget to add the uv_vir register field for it.
Change-Id: Ie27216d0612d41fec02346ce65412207ed26d4a1
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9157349/)
This misc update would try to fix below comments from my eDP thread[0],
and lucky to say this version is stable, and i'm start to perpare the
pull request to David with this version. So i guess it's time to create
a misc FIXUP patch to address the comments.
[0]: https://patchwork.kernel.org/patch/9175613/
- Correct the misspell of "marcos" in commit message (Dominik, reviewed at Google Gerrit)
- Write a kerneldoc-style comment explaining the chips data fields (Tomasz, reviewed at Google Gerrit)
- Drop the '.lcdcsel_mask' number in chips data field (Tomasz, reviewed at Google Gerrit)
- Make this hack code more clear (Tomasz, reviewed at Google Gerrit)
reg = ~reg & REF_CLK_MASK; ---> reg ^= REF_CLK_MASK;
- Give the "rk3399-edp" a separate line for clarity in document (Tomasz, reviewed at Google Gerrit)
- Move 'output_type' setting before the return statement (Tomasz, reviewed at Google Gerrit)
- Avoid to change any internal driver state in .mode_valid interface. (Tomasz, reviewed at Google Gerrit)
- Hook the connector's color_formats in .get_modes directly. (Tomasz, reviewed at Google Gerrit)
Change-Id: Ic35f166ebac04e417ff3d135e7bf4573bbca2004
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This patch adds a helper to parse the encoder endpoint connected to the
encoder's crtc and two helpers to return its id and port id.
This can be used to determine input mux setting from endpoint or port ids.
Change-Id: I48eb7c66edb951af40085e4e388afbd5d4b2c77b
Suggested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
(cherry pick from commit 4cacf91fcb)
