In OS descriptors handling, if ctrl->bRequestType is USB_RECIP_DEVICE
and w_index != 0x4 or (w_value >> 8) is true, it will not reset
req->length, but use the default value(-EOPNOTSUPP), and queue an
OS desc request with an invalid req->length. It always happens
on the platforms which use os_desc(for example: rk3366,rk3399),
and cause kernel panic as follows(use dwc3 driver):
Unable to handle kernel paging request at virtual address ffffffc0f7e00000
Internal error: Oops: 96000146 [#1] PREEMPT SMP
PC is at __dma_clean_range+0x18/0x30
LR is at __swiotlb_map_page+0x50/0x64
Call trace:
[<ffffffc0000930f8>] __dma_clean_range+0x18/0x30
[<ffffffc00062214c>] usb_gadget_map_request+0x134/0x1b0
[<ffffffc0005c289c>] __dwc3_ep0_do_control_data+0x110/0x14c
[<ffffffc0005c2d38>] __dwc3_gadget_ep0_queue+0x198/0x1b8
[<ffffffc0005c2e18>] dwc3_gadget_ep0_queue+0xc0/0xe8
[<ffffffc00061cfec>] composite_ep0_queue.constprop.14+0x34/0x98
[<ffffffc00061dfb0>] composite_setup+0xf60/0x100c
[<ffffffc0006204dc>] android_setup+0xd8/0x138
[<ffffffc0005c29a4>] dwc3_ep0_delegate_req+0x34/0x50
[<ffffffc0005c3534>] dwc3_ep0_interrupt+0x5dc/0xb58
[<ffffffc0005c0c3c>] dwc3_thread_interrupt+0x15c/0xa24
With this patch, the gadget driver will not queue a request and
return immediately if req->length is invalid. And the usb controller
driver can handle the unsupport request correctly.
Change-Id: I60270d7c12fa190a99cd1079880a2f7167e7af27
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This patch fixes following compile error in dwc3 if select
CONFIG_USB_DWC3_HOST.
drivers/usb/dwc3/core.c:874: undefined reference to `dwc3_gadget_restart'
drivers/usb/dwc3/core.c:880: undefined reference to `dwc3_gadget_restart'
which was caused by commit
commit 9607f47dfe
usb: dwc3: add functions to set force mode
Change-Id: Id0abaf89fba006609dbf2e7a771149453465b371
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This adds thermal zone node to rk3399 dtsi, rk3399 thermal data is
including the cpu and gpu sensor zone node.
At the moment, remove the rk3368 thermal data from rk399 dtsi.
The thermal zone node is the node containing all the required info
for describing a thermal zone, including its cooling device bindings. The
thermal zone node must contain, apart from its own properties, one sub-node
containing trip nodes and one sub-node containing all the zone cooling maps
The following is the parameter is introduced:
* polling-delay:
The maximum number of milliseconds to wait between polls
* polling-delay-passive:
The maximum number of milliseconds to wait between polls when performing
passive cooling.
* trips:
A sub-node which is a container of only trip point nodes required to describe
the thermal zone.
* cooling-maps:
A sub-node which is a container of only cooling device map nodes, used to
describe the relation between trips and cooling devices.
* cooling-device:
A phandle of a cooling device with its specifier, referring to which cooling
device is used in this cooling specifier binding. In the cooling specifier,
the first cell is the minimum cooling state and the second cell is the maximum
cooling state used in this map.
Change-Id: I76c5829fdc120cd5da078e2937abeee720ee379c
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Whenever the current temperature is updated, the trip points immediately
below and above the current temperature are found. A sensor driver
callback `set_trips' is then called with the temperatures.
Lastly, The sensor will trigger the hardware high temperature interrupts
to increase the sampleing rate and throttle frequency to limit the temperature
rising When performing passive cooling.
Change-Id: I43d37a8431240cb7b62da7bff83464aba3c8983e
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This adds support for hardware-tracked trip points to the device tree
thermal sensor framework.
The framework supports an arbitrary number of trip points. Whenever
the current temperature is updated, the trip points immediately
below and above the current temperature are found. A sensor driver
callback `set_trips' is then called with the temperatures.
If there is no trip point above or below the current temperature,
the passed trip temperature will be LONG_MAX or LONG_MIN respectively.
In this callback, the driver should program the hardware such that
it is notified when either of these trip points are triggered.
When a trip point is triggered, the driver should call
`thermal_zone_device_update' for the respective thermal zone. This
will cause the trip points to be updated again.
If the `set_trips' callback is not implemented (is NULL), the framework
behaves as before.
CQ-DEPEND=CL:*210768
BUG=chrome-os-partner:30834
TEST=None
Change-Id: I33226d2b80f3e71a0c3ca3fbc5718db4e461268f
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Signed-off-by: Wei Ni <wni@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/212425
Reviewed-by: Olof Johansson <olofj@chromium.org>
Commit-Queue: Olof Johansson <olofj@chromium.org>
Tested-by: Olof Johansson <olofj@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/210454
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/267514
Tested-by: David Riley <davidriley@chromium.org>
Reviewed-by: David Riley <davidriley@chromium.org>
Commit-Queue: David Riley <davidriley@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(cherry-picked from https://chromium.googlesource.com/chromiumos/
third_party/kernel/+/v3.18 commit 397befabb2a52fc16586509a970f8c98268b8040)
We need the cpu throttle and IPA function for rockchip.
Also enable the writable trips function.
Let's enable the needed config for thermal.
Change-Id: Ibd43aa4ef3cc5e0a325e376d753cffc8bcdb8c02
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The endpoint order would decide the priority of connector devices,
the higher the priority ranking.
For now eDP can't light up with VOP Lit, so we need to cut down
the priority that eDP in VOP Lit, and raise up the priority that
MIPI in VOP Lit.
Change-Id: Ide4e321f03cf7ad5080c6db7f9230962963a3eb8
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This is a hack way to let VOP Big to select eDP device when VOP
Big and Lit all enabled.
Change-Id: Ia2bc91ff903bbc7d00deed57aab315328ce54378
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Fix a typo making the clk_cifout access a
wrong clk tree to handle its mux and div.
Change-Id: Ief20e684eadd10b75cf36120df16f13c7581d303
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Panel brightness is controller by EC, the AP just enable/disable the
backlight power through GPIO1_C1.
Change-Id: I46e1f3b5098159cb07f86ba203ef8cfa102dd385
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The RK3399 EVB board is using the LG LP097QX1-SPA1
9.7" 2048x1536 eDP panel.
Change-Id: I837b0a569605591756918b12f56dbaa0b1f3f8d4
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Until we get PWM regulator solid, let's hack it out and just keep
whatever the firmware set for us.
Note that when the kernel boots it appears that it does some reparenting
of clocks and the PWM frequency actually changes. ...but the voltage
seems OK ish.
Change-Id: I3be6ea4460f685e4a75a0f7f31f767f09b908442
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254650
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(Fixes the typo)
the hw default of the dvs2 is pull up which is not correct.
set the dvs2 gpio pull down.
Change-Id: I0d296cecc422456cb72630d5ce64a5c7e5dad283
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Until we get all the magic PWM regulator stuff solved with Boris's
wonderful upstream patches, let's just hack the PWM clock to be critical
so it never turns off. Nuff said.
Change-Id: I99660b0b188413eb08030a3ae87c045c338b30db
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254649
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(Fixes the pclk_rkpwm_pmu into pmucru_critical_clock)
We should make sure the config generate from the savedefconfig.
Okay, anyway cleanup the config with run 'make ARCH=arm64 savedefconfig'.
Change-Id: Ia094322870d378183760e32b7177971342e48439
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The eDP panel of Kevin board only have a AP GPIO to control
the backlight power, so we need to enable the GPIO backlight
type for it.
Change-Id: I939e1c658b56ee5d889af820985f9ffd46f50485
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD
panel connected using eDP interfaces.
Change-Id: Ib5164763d18c5cffcc83b38715f559a4a0c02638
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel
connected using eDP interfaces.
Change-Id: I3c2208fc45b53b0fab328fcb9ba204f610a9f9f6
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
AFAIK, the hardware designed that TSHUT should be set the active high.
Since rk3399 evb designed the over-temperature protection pin is
connected to PMIC that active high vaild.
Also, as gru/kevin designed the over-temperature protection pin is
connected to EC control that active high to prevent leakage.
Change-Id: Ib7b15d115d2ea4e474918fc416dde273b040e740
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The hardware IC designed that VOP must output the RGB10 video format to
eDP contoller, and if eDP panel only support RGB8, then eDP contoller
should cut down the video data, not via VOP contoller, that's why we need
to hardcode the VOP output mode to RGA10 here.
Change-Id: I733eae8a5dda51c0288d8627ceffb39a2f804e62
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Rockchip VOP couldn't output YUV video format for eDP controller, so
when driver detect connector support YUV video format, we could hack
it down to RGB888.
Change-Id: Ia876bb49e772f85bef201af2b62dd558d6b99257
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
It's helpful to expand the mode_valid callback to platform driver,
so they could valid the display mode or informations.
Change-Id: Icfd7593bd10c93fc9045acf04a8d0ed6336ffb85
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Some boards don't need to declare a panel device node, like the
display interface is DP monitors, so it's necessary to make the
panel detect to an optional action.
Change-Id: I0146e9f9fb2e35b5878ab114e8aa1df35ba4843d
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
On RK3399 EVB board, the LG panel only support RGB888. so with previous
changes, VOP would send the RGB10 video format to panel, and then panel
just display abnormally.
This reverts commit 144e62cef3.
Change-Id: I09a5ab0aa8758e87e8b7f2fc20fbbaa113fe1d33
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
It looks like the addition of default-sample-phase to the GRU dts is
what was causing my periodic boot failures. After removing it I found
that I could get 25+ reboots with no failures. Calling it good.
BUG=None
TEST=Reboot many times; see successful boot each time.
Change-Id: Id200957da9d9a2eb81ce63dcb57c4f0f5e94e72d
Signed-off-by: Douglas Anderson <dianders@chromium.org>
To update the notes for keeping in mind that quickly in case
someone re-read this driver in the future.
Change-Id: Ic752ed1d6a818f21560befd981383e8b532dff36
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The interleave is between power down and start of conversion,
This patch adds to workaround ic time sync issue for control.
Change-Id: Ib9f28fd92bcecf8ddaa8a69d47ced87fef04e7c6
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The RK3366 SoCs have two Temperature Sensors, channel 0 is for CPU
channel 1 is for GPU.
Change-Id: I71324c65e82804f52d464b986e1d86127f8dc040
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Normally, the display regulator would be kept powered on by the
display/backlight driver, but we don't yet have a DT representation or
driver for this, as the PWM is controlled by the EC. Just force the
regulator on for now.
This wasn't needed on some boards yet, since they were forcing this
regulator "on." But for those where we might be controlling it, we need
this. (And it's harmless otherwise.)
This is necessary but not sufficient for getting UI up on my board.
Change-Id: I30650c178dd42d76542f8f2491e22d9bf548363e
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254935
Commit-Queue: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Stephen Barber <smbarber@google.com>
Now, we can playback and capture via DA7219 machine driver call the
da7219_aad_jack_det (simple-card can not do this).
Change-Id: I8b1be189031f875b1c5328e9357115761a5f4da3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The DA7219 only support headphone playback, we may not call the
da7219_aad_jack_det when we use the simple-card.
Therefore, the machine driver may be need to submit upstream.
Change-Id: Iecf53fa62fcaf43175bbbcd2b7c8b0d5c67655ac
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We recommend, VOP0 is the main screen, VOP1 is a sub screen,
only VOP0 is able to re-set parent (VPLL) rate.
Change-Id: If40f95ce18e73477df8f7f031013333a603d5eb2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Because frac div need to more than 20 multiple between the numerator
and denominator, but we need to be fit many HDMI/DP freqs and may
bring serious jitter when the dclk_vopx below the dclk_vopx_frac.
Therefore, we can select dclk_vopx below the dclk_vopx_div directly.
Change-Id: If3d9051211f0b160a507f0942667796f043f4ec2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
By default the device latches data on the falling edge of the
BCLK in DSP mode, whereas the expectation for normal BCLK is to
latch on the rising edge. This updates the driver to invert the
BCLK configuration for DSP mode, to align with expected behaviour.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 4acfa36be6)
Change-Id: I646f6ec9fb377ce95d90d57c80dc05f13b6696f2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Initial silicon did not have master bias enabled by default, unlike
later HW, so use regmap patch to align with newer defaults.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit abd7c894fc)
Change-Id: I1b941c779320b58110b78c2c127bb08629c7a3fa
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
PLL mode based on 32KHz master clock not supported in
AB silicon so remove support from the driver.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 501f72e9c5)
Change-Id: Ie3e3388af33a74fca6bf60405e1b54b860b43f18
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
HW can provide 1.6V micbias level as well the existing levels
already provided in the driver. This patch adds support for 1.6V
to the DT binding.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 0aed64c176)
Change-Id: I714fb76154242aa6392143ebe8db20a7510b45a3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
