Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the pmugrf.
Use MUXPMUGRF() to cover this special clock-type.
Change-Id: Iac962a27a3c88ce188d03c416cb4b3b45a462c0a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
1.don't update vpc when record vpc equals 0 in gc progress
2.increase the number of read retry
3.avoid danger of abnormal power lost
4.change flash_read_page_raw return to error_ecc_bits
5.add nand buildin ecc support
6.skip ECC error page instead of marking as bad block
7.adjust the way of building tables to increase ftl init
Change-Id: I9ba24980c06d61a5a1d66019378075e0171a5887
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
CEA-861-F tells us:
"When transmitting any RGB colorimetry, the Source should set the
YQ-field to match the RGB Quantization Range being transmitted
(e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
set YQ=1) and the Sink shall ignore the YQ-field."
So let's go ahead and do that. Perhaps there are sinks that don't
ignore the YQ as they should for RGB?
I wasn't able to find similar text in CEA-861-E, so it would seem
to be a fairly "recent" addition.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170111125725.8086-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit fcc8a22cc9)
Change-Id: I355b86175d2b33e88bd384a01f7e6378b21d13fd
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
HDMI 2.0 recommends that we set the Q bits in the AVI infoframe
even when the sink does not support quantization range selection (QS=0).
According to CEA-861 we can do that as long as the Q we send matches
the default quantization range for the mode.
Previously I think I had misread the spec as saying that you can't
send a non-zero Q at all when QS=0. But that's not what the spec
actually says.
v2: Fix typo in commit message (Jani)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170111125725.8086-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 779c4c2866)
Change-Id: Ic006e2a2a9ac2f1ab105c595bc4a62c0918c6dff
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Some logs may appear before tee-supplicant start,
so uart port config should be done as early as possible.
Change-Id: I51bdb6a9d0f5160a6dc66ad015577a77df6897b4
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
Kernel is running in secure mode on some platforms(e.g. rk3128/rv1108),
which has no secure OS to support TEE service.
Change-Id: I275413230b2a8ec3864fc5a5ba043a155d724ced
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
The address@88000000 is out of memory on rk3128-fireprime, so remove
the cma region@88000000, just delete the property <reg>, so that
system will alloc cma region automatically.
Change-Id: I2b9fdf1cd19d9fcecd59421fd551d709f9054cae
Signed-off-by: Liang Chen <cl@rock-chips.com>
The RK3399 sapphire board hasn't use dvs2 of pmic rk808,
remove it from dts.
Change-Id: I6b18f2ac48d2f32ba53cc6f16303be0f42d74fe5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
ttyS2 and fiq debugger don't use the same uart2
Change-Id: I442bb34a5a9a7c836b01b693b199b82284539ca6
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
ttyS2 and fiq debugger don't use the same uart2
Change-Id: Id93080187e99089b590cdd29e98713d4e2b50dee
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
ttyS4 and fiq debugger don't use the same uart4
Change-Id: I9e73cd663b5a16615e727d65d3e67a2368390615
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
ttyS2 and fiq debugger don't use the same uart2
Change-Id: I4ca2df8a763f0dba7a28cd9b8e2b32e885feaa0b
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
ttyS2 and fiq debugger don't use the same uart2
Change-Id: I40fc4010624abf6b687bc56b739b81b992f9d61a
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
ttyS2 and fiq debugger don't use the same uart2
Change-Id: Id726872e68ef873a77b0a5bf5c60f0525f789b0f
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
ttyS2 and fiq debugger don't use the same uart2
Change-Id: I9c6b26c51174e86621fd8369d9231c7b4d20c89f
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
ttyS2 and fiq debugger don't use the same uart2
Change-Id: Ia178159f240b30abe29312c8dd94ab4711834bbf
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
ttyS2 and fiq debugger don't use the same uart2
Change-Id: Ibb9db5ff84d334d77787ea6f39a0802ba489781c
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
ttyS2 and fiq debugger don't use the same uart2
Change-Id: Ic6d2aa936586869197101593ac9b8056be128406
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Someone may enable uart2 and fiq debugger, which is illegal.
&uart2 {
status = "okay";
};
&fiq_debugger {
status = "okay";
};
Change-Id: Ibecd3c3ca69de1216103d7c373a4d282cf93cb30
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Maybe you need to use uart2 as normal ttyS2, firstly disable the
uart2 debug function. Set "rockchip,serial-id" as -1, it means
fiq debugger still have a /dev/ttyFIQ0, but it doesn't have any uart
hardware.
&fiq_debugger {
rockchip,serial-id = <0xffffffff>;
status = "okay";
};
Change-Id: I80065eed852eb50139520c5c1fdceb882773d79d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
If the enable-gpios property of a simple panel in device tree is set,
the GPIO is not toggled on/off because of missing calls to
drm_panel_prepare and drm_panel_unprepare.
Change-Id: I0a191c8bdd05ef8c2d3d41259937cb5ad0b29f08
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
DPTX implements the programmable SSC down-spreading with up to
0.5% modulation amplitude and 30k/33k modulation frequency.
Change-Id: I2c3eae8f27c84eb1b22eac8973691e0276c1588e
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
