Commit Graph

979789 Commits

Author SHA1 Message Date
Marc Zyngier
663bbfa2a4 UPSTREAM: KVM: arm64: Set the MTE tag bit before releasing the page
Setting a page flag without holding a reference to the page
is living dangerously. In the tag-writing path, we drop the
reference to the page by calling kvm_release_pfn_dirty(),
and only then set the PG_mte_tagged bit.

It would be safer to do it the other way round.

Fixes: f0376edb1d ("KVM: arm64: Add ioctl to fetch/store tags in a guest")
Cc: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/87k0mjidwb.wl-maz@kernel.org
(cherry picked from commit 98db7259fa)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Iea5ad082147127c19a580c98629ac60c696092f8
2021-07-13 16:09:17 +01:00
Steven Price
71c05826d6 BACKPORT: KVM: arm64: Document MTE capability and ioctl
A new capability (KVM_CAP_ARM_MTE) identifies that the kernel supports
granting a guest access to the tags, and provides a mechanism for the
VMM to enable it.

A new ioctl (KVM_ARM_MTE_COPY_TAGS) provides a simple way for a VMM to
access the tags of a guest without having to maintain a PROT_MTE mapping
in userspace. The above capability gates access to the ioctl.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-7-steven.price@arm.com
(cherry picked from commit 04c02c201d)
[willdeacon@: Dropped missing context]
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I489a4cc12cad2b4664b131d4d65c9d12024eaa48
2021-07-13 16:09:17 +01:00
Steven Price
6743a619b2 UPSTREAM: KVM: arm64: Add ioctl to fetch/store tags in a guest
The VMM may not wish to have it's own mapping of guest memory mapped
with PROT_MTE because this causes problems if the VMM has tag checking
enabled (the guest controls the tags in physical RAM and it's unlikely
the tags are correct for the VMM).

Instead add a new ioctl which allows the VMM to easily read/write the
tags from guest memory, allowing the VMM's mapping to be non-PROT_MTE
while the VMM can still read/write the tags for the purpose of
migration.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-6-steven.price@arm.com
(cherry picked from commit f0376edb1d)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I2f1ea19d9f2bdbdd3025934b770468b1404020c6
2021-07-13 16:09:17 +01:00
Steven Price
f8e7a57629 UPSTREAM: KVM: arm64: Expose KVM_ARM_CAP_MTE
It's now safe for the VMM to enable MTE in a guest, so expose the
capability to user space.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-5-steven.price@arm.com
(cherry picked from commit 673638f434)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I791fb69fa2ad6fc37b564ba156c654771c760cae
2021-07-13 16:09:16 +01:00
Steven Price
0fcdf88b97 UPSTREAM: KVM: arm64: Save/restore MTE registers
Define the new system registers that MTE introduces and context switch
them. The MTE feature is still hidden from the ID register as it isn't
supported in a VM yet.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-4-steven.price@arm.com
(cherry picked from commit e1f358b504)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I4785c794d1725f88186e5bb014552d08501ad4f0
2021-07-13 16:09:16 +01:00
Steven Price
fe7e960474 BACKPORT: KVM: arm64: Introduce MTE VM feature
Add a new VM feature 'KVM_ARM_CAP_MTE' which enables memory tagging
for a VM. This will expose the feature to the guest and automatically
tag memory pages touched by the VM as PG_mte_tagged (and clear the tag
storage) to ensure that the guest cannot see stale tags, and so that
the tags are correctly saved/restored across swap.

Actually exposing the new capability to user space happens in a later
patch.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
[maz: move VM_SHARED sampling into the critical section]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-3-steven.price@arm.com
(cherry picked from commit ea7fc1bb1c)
[willdeacon@: Torrid time resolving mmu.c, as upstream merge commit made
              significant changes to the original patch. Fixed UAPI
	      definitions in kvm.h]
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: If584166e765413456575f642f87003a4c9e41280
2021-07-13 16:09:16 +01:00
Steven Price
8c77a643d0 UPSTREAM: arm64: mte: Sync tags for pages where PTE is untagged
A KVM guest could store tags in a page even if the VMM hasn't mapped
the page with PROT_MTE. So when restoring pages from swap we will
need to check to see if there are any saved tags even if !pte_tagged().

However don't check pages for which pte_access_permitted() returns false
as these will not have been swapped out.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210621111716.37157-2-steven.price@arm.com
(cherry picked from commit 69e3b846d8)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I2232daa13de3354acc2b487373977950847b0b41
2021-07-13 16:09:16 +01:00
Marc Zyngier
ad6d82f467 UPSTREAM: KVM: arm64: Restore PMU configuration on first run
Restoring a guest with an active virtual PMU results in no perf
counters being instanciated on the host side. Not quite what
you'd expect from a restore.

In order to fix this, force a writeback of PMCR_EL0 on the first
run of a vcpu (using a new request so that it happens once the
vcpu has been loaded). This will in turn create all the host-side
counters that were missing.

Reported-by: Jinank Jain <jinankj@amazon.de>
Tested-by: Jinank Jain <jinankj@amazon.de>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/87wnrbylxv.wl-maz@kernel.org
Link: https://lore.kernel.org/r/b53dfcf9bbc4db7f96154b1cd5188d72b9766358.camel@amazon.de
(cherry picked from commit d0c94c4979)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Iea80f33fa2fe35cae30e0ea370bde52d127ccda8
2021-07-13 16:09:16 +01:00
Alexandru Elisei
4010ce1626 UPSTREAM: KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
1 has the following effect:

"Reset all event counters accessible in the current Exception level, not
including PMCCNTR_EL0, to zero."

Similar behaviour is described for AArch32 on page G8-7022. Make it so.

Fixes: c01d6a1802 ("KVM: arm64: pmu: Only handle supported event counters")
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210618105139.83795-1-alexandru.elisei@arm.com
(cherry picked from commit 2a71fabf6a)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I47d26a718844563278a5f820452d85a773452f58
2021-07-13 16:09:16 +01:00
Yanan Wang
ab687fde9a BACKPORT: KVM: arm64: Move guest CMOs to the fault handlers
We currently uniformly perform CMOs of D-cache and I-cache in function
user_mem_abort before calling the fault handlers. If we get concurrent
guest faults(e.g. translation faults, permission faults) or some really
unnecessary guest faults caused by BBM, CMOs for the first vcpu are
necessary while the others later are not.

By moving CMOs to the fault handlers, we can easily identify conditions
where they are really needed and avoid the unnecessary ones. As it's a
time consuming process to perform CMOs especially when flushing a block
range, so this solution reduces much load of kvm and improve efficiency
of the stage-2 page table code.

We can imagine two specific scenarios which will gain much benefit:
1) In a normal VM startup, this solution will improve the efficiency of
handling guest page faults incurred by vCPUs, when initially populating
stage-2 page tables.
2) After live migration, the heavy workload will be resumed on the
destination VM, however all the stage-2 page tables need to be rebuilt
at the moment. So this solution will ease the performance drop during
resuming stage.

Reviewed-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210617105824.31752-5-wangyanan55@huawei.com
(cherry picked from commit 25aa28691b)
[willdeacon@: Fix conflicts due to lack of gfn-based spte notifiers]
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I8fb827c24f57e2c1bcb0a016729bda9a72eaa389
2021-07-13 16:09:15 +01:00
Yanan Wang
7a2b91fd87 BACKPORT: KVM: arm64: Tweak parameters of guest cache maintenance functions
Adjust the parameter "kvm_pfn_t pfn" of __clean_dcache_guest_page
and __invalidate_icache_guest_page to "void *va", which paves the
way for converting these two guest CMO functions into callbacks in
structure kvm_pgtable_mm_ops. No functional change.

Reviewed-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210617105824.31752-4-wangyanan55@huawei.com
(cherry picked from commit 378e6a9c78)
[willdeacon@: Fix conflicts with cache maintenance rework and lack of gfn-based
              spte notifiers]
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Ic6c4de33e005ec6fdefd91985485ed2c22b0271c
2021-07-13 16:09:15 +01:00
Yanan Wang
4c3461fa58 UPSTREAM: KVM: arm64: Introduce mm_ops member for structure stage2_attr_data
Also add a mm_ops member for structure stage2_attr_data, since we
will move I-cache maintenance for guest stage-2 to the permission
path and as a result will need mm_ops for some callbacks.

Reviewed-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210617105824.31752-3-wangyanan55@huawei.com
(cherry picked from commit a4d5ca5c7c)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Ie46f53b669a579856e29df6a3155c466bd41aa83
2021-07-13 16:09:15 +01:00
Yanan Wang
b547d2b80f UPSTREAM: KVM: arm64: Introduce two cache maintenance callbacks
To prepare for performing CMOs for guest stage-2 in the fault handlers
in pgtable.c, here introduce two cache maintenance callbacks in struct
kvm_pgtable_mm_ops. We also adjust the comment alignment for the
existing part but make no real content change at all.

Reviewed-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
[maz: fixed up comments and renamed callbacks]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210617105824.31752-2-wangyanan55@huawei.com
(cherry picked from commit 6204004de3)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: If5bb0706b081c16b3e9853954866c4c81030b8a9
2021-07-13 16:09:15 +01:00
Quentin Perret
ce9bce48a9 UPSTREAM: KVM: arm64: Use less bits for hyp_page refcount
The hyp_page refcount is currently encoded on 4 bytes even though we
never need to count that many objects in a page. Make it 2 bytes to save
some space in the vmemmap.

As overflows are more likely to happen as well, make sure to catch those
with a BUG in the increment function.

Signed-off-by: Quentin Perret <qperret@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210608114518.748712-8-qperret@google.com
(cherry picked from commit 6929586d8e)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I1e36b015fc65b45b811a886607e9aa3bce873e27
2021-07-13 16:09:15 +01:00
Quentin Perret
05d7d55b07 UPSTREAM: KVM: arm64: Use less bits for hyp_page order
The hyp_page order is currently encoded on 4 bytes even though it is
guaranteed to be smaller than this. Make it 2 bytes to reduce the hyp
vmemmap overhead.

Signed-off-by: Quentin Perret <qperret@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210608114518.748712-7-qperret@google.com
(cherry picked from commit 87ec060673)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I0a5216e4f97eecaf74854206386d80a204624760
2021-07-13 16:09:15 +01:00
Quentin Perret
1fa2ff5d16 UPSTREAM: KVM: arm64: Remove hyp_pool pointer from struct hyp_page
Each struct hyp_page currently contains a pointer to a hyp_pool struct
where the page should be freed if its refcount reaches 0. However, this
information can always be inferred from the context in the EL2 code, so
drop the pointer to save a few bytes in the vmemmap.

Signed-off-by: Quentin Perret <qperret@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210608114518.748712-6-qperret@google.com
(cherry picked from commit d978b9cfe6)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Iadcbf118f2c9d7651e631ffb46393e2dbfbfc58b
2021-07-13 16:09:15 +01:00
Quentin Perret
b6d67813c1 UPSTREAM: KVM: arm64: Unify MMIO and mem host stage-2 pools
We currently maintain two separate memory pools for the host stage-2,
one for pages used in the page-table when mapping memory regions, and
the other to map MMIO regions. The former is large enough to map all of
memory with page granularity and the latter can cover an arbitrary
portion of IPA space, but allows to 'recycle' pages.

However, this split makes accounting difficult to manage as pages at
intermediate levels of the page-table may be used to map both memory and
MMIO regions. Simplify the scheme by merging both pools into one. This
means we can now hit the -ENOMEM case in the memory abort path, but
we're still guaranteed forward-progress in the worst case by unmapping
MMIO regions. On the plus side this also means we can usually map a lot
more MMIO space at once if memory ranges happen to be mapped with block
mappings.

Signed-off-by: Quentin Perret <qperret@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210608114518.748712-5-qperret@google.com
(cherry picked from commit 7c350ea39e)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I0fbab059f0c01287f2074392391259092e55cf48
2021-07-13 16:09:14 +01:00
Quentin Perret
9e4a41b768 UPSTREAM: KVM: arm64: Remove list_head from hyp_page
The list_head member of struct hyp_page is only needed when the page is
attached to a free-list, which by definition implies the page is free.
As such, nothing prevents us from using the page itself to store the
list_head, hence reducing the size of the vmemmap.

Signed-off-by: Quentin Perret <qperret@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210608114518.748712-4-qperret@google.com
(cherry picked from commit 914cde58a0)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I6055802715da653caab20da16f9a33d777de3acf
2021-07-13 16:09:14 +01:00
Quentin Perret
c373a2f4aa UPSTREAM: KVM: arm64: Use refcount at hyp to check page availability
The hyp buddy allocator currently checks the struct hyp_page list node
to see if a page is available for allocation or not when trying to
coalesce memory. Now that decrementing the refcount and attaching to
the buddy tree is done in the same critical section, we can rely on the
refcount of the buddy page to be in sync, which allows to replace the
list node check by a refcount check. This will ease removing the list
node from struct hyp_page later on.

Signed-off-by: Quentin Perret <qperret@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210608114518.748712-3-qperret@google.com
(cherry picked from commit 581982decc)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I7a985eaf0665da27fd35e55701098241b63de7c9
2021-07-13 16:09:14 +01:00
Quentin Perret
b3d465e641 UPSTREAM: KVM: arm64: Move hyp_pool locking out of refcount helpers
The hyp_page refcount helpers currently rely on the hyp_pool lock for
serialization. However, this means the refcounts can't be changed from
the buddy allocator core as it already holds the lock, which means pages
have to go through odd transient states.

For example, when a page is freed, its refcount is set to 0, and the
lock is transiently released before the page can be attached to a free
list in the buddy tree. This is currently harmless as the allocator
checks the list node of each page to see if it is available for
allocation or not, but it means the page refcount can't be trusted to
represent the state of the page even if the pool lock is held.

In order to fix this, remove the pool locking from the refcount helpers,
and move all the logic to the buddy allocator. This will simplify the
removal of the list node from struct hyp_page in a later patch.

Signed-off-by: Quentin Perret <qperret@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210608114518.748712-2-qperret@google.com
(cherry picked from commit 6cbf874e51)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I3fc3296d2cce2c20bed530dbc3ee856f7b27efe3
2021-07-13 16:09:14 +01:00
Keqian Zhu
086f9045f1 UPSTREAM: KVM: arm64: Try stage2 block mapping for host device MMIO
The MMIO region of a device maybe huge (GB level), try to use
block mapping in stage2 to speedup both map and unmap.

Compared to normal memory mapping, we should consider two more
points when try block mapping for MMIO region:

1. For normal memory mapping, the PA(host physical address) and
HVA have same alignment within PUD_SIZE or PMD_SIZE when we use
the HVA to request hugepage, so we don't need to consider PA
alignment when verifing block mapping. But for device memory
mapping, the PA and HVA may have different alignment.

2. For normal memory mapping, we are sure hugepage size properly
fit into vma, so we don't check whether the mapping size exceeds
the boundary of vma. But for device memory mapping, we should pay
attention to this.

This adds get_vma_page_shift() to get page shift for both normal
memory and device MMIO region, and check these two points when
selecting block mapping size for MMIO region.

Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210507110322.23348-3-zhukeqian1@huawei.com
(cherry picked from commit 2aa53d68ce)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I1af0ba01c521d3a3c66301f32fdc3f780f10fe6f
2021-07-13 16:09:14 +01:00
Keqian Zhu
9638b8c092 UPSTREAM: KVM: arm64: Remove the creation time's mapping of MMIO regions
The MMIO regions may be unmapped for many reasons and can be remapped
by stage2 fault path. Map MMIO regions at creation time becomes a
minor optimization and makes these two mapping path hard to sync.

Remove the mapping code while keep the useful sanity check.

Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210507110322.23348-2-zhukeqian1@huawei.com
(cherry picked from commit fd6f17bade)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I428bd02d7cb83f4f48d5e294c0be9f09fb15fae4
2021-07-13 16:09:14 +01:00
Marc Zyngier
ccaf192edd UPSTREAM: KVM: arm64: timer: Add support for SW-based deactivation
In order to deal with the lack of active state, we need to use
the mask/unmask primitives (after all, the active state is just an
additional mask on top of the normal one).

To avoid adding a bunch of ugly conditionals in the timer and vgic
code, let's use a timer-specific irqdomain to deal with the state
conversion. Yes, this is an unexpected use of irqdomains, but
there is no reason not to be just as creative as the designers
of the HW...

This involves overloading the vcpu_affinity, set_irqchip_state
and eoi callbacks so that the rest of the KVM code can continue
ignoring the oddities of the underlying platform.

Signed-off-by: Marc Zyngier <maz@kernel.org>
(cherry picked from commit 5f59229680)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I53ec1b772615e0edc1dfec20350b0a330be2f59a
2021-07-13 16:09:13 +01:00
Marc Zyngier
311055c4a5 UPSTREAM: KVM: arm64: timer: Refactor IRQ configuration
As we are about to add some more things to the timer IRQ
configuration, move this code out of the main timer init code
into its own set of functions.

No functional changes.

Signed-off-by: Marc Zyngier <maz@kernel.org>
(cherry picked from commit 2f2f7e39db)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Ifa99e1f81cff43356f5e21d583d08cabff7f0ba7
2021-07-13 16:09:13 +01:00
Marc Zyngier
bdd049f8d1 UPSTREAM: KVM: arm64: vgic: Implement SW-driven deactivation
In order to deal with these systems that do not offer HW-based
deactivation of interrupts, let implement a SW-based approach:

- When the irq is queued into a LR, treat it as a pure virtual
  interrupt and set the EOI flag in the LR.

- When the interrupt state is read back from the LR, force a
  deactivation when the state is invalid (neither active nor
  pending)

Interrupts requiring such treatment get the VGIC_SW_RESAMPLE flag.

Signed-off-by: Marc Zyngier <maz@kernel.org>
(cherry picked from commit 354920e794)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Ic6d9c96f989e90cd6b7e55f0919f3e914520faaa
2021-07-13 16:09:13 +01:00
Marc Zyngier
145d87ff19 UPSTREAM: KVM: arm64: vgic: move irq->get_input_level into an ops structure
We already have the option to attach a callback to an interrupt
to retrieve its pending state. As we are planning to expand this
facility, move this callback into its own data structure.

This will limit the size of individual interrupts as the ops
structures can be shared across multiple interrupts.

Signed-off-by: Marc Zyngier <maz@kernel.org>
(cherry picked from commit db75f1a33f)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I6176af86588b144158cf62f5a10201e9ff5cd6c4
2021-07-13 16:09:13 +01:00
Marc Zyngier
9abc158d3c UPSTREAM: KVM: arm64: vgic: Let an interrupt controller advertise lack of HW deactivation
The vGIC, as architected by ARM, allows a virtual interrupt to
trigger the deactivation of a physical interrupt. This allows
the following interrupt to be delivered without requiring an exit.

However, some implementations have choosen not to implement this,
meaning that we will need some unsavoury workarounds to deal with this.

On detecting such a case, taint the kernel and spit a nastygram.
We'll deal with this in later patches.

Signed-off-by: Marc Zyngier <maz@kernel.org>
(cherry picked from commit f6c3e24fb7)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I00244ba04b9671eb27be0b1d566969e3dc921da6
2021-07-13 16:09:13 +01:00
Marc Zyngier
6873a8ecc4 UPSTREAM: KVM: arm64: vgic: Be tolerant to the lack of maintenance interrupt masking
As it turns out, not all the interrupt controllers are able to
expose a vGIC maintenance interrupt that can be independently
enabled/disabled.

And to be fair, it doesn't really matter as all we require is
for the interrupt to kick us out of guest mode out way or another.

To that effect, add gic_kvm_info.no_maint_irq_mask for an interrupt
controller to advertise the lack of masking.

Signed-off-by: Marc Zyngier <maz@kernel.org>
(cherry picked from commit 669062d2a1)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I06c247347faf9899aedc131e95b6f764aa474f64
2021-07-13 16:09:13 +01:00
Marc Zyngier
fe77b6dd3a UPSTREAM: KVM: arm64: Handle physical FIQ as an IRQ while running a guest
As we we now entertain the possibility of FIQ being used on the host,
treat the signalling of a FIQ while running a guest as an IRQ,
causing an exit instead of a HYP panic.

Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
(cherry picked from commit 74501499d4)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: If83a70cff22464133f516ccc03ee13483121b802
2021-07-13 16:09:13 +01:00
Marc Zyngier
7a95be2082 UPSTREAM: irqchip/gic: Split vGIC probing information from the GIC code
The vGIC advertising code is unsurprisingly very much tied to
the GIC implementations. However, we are about to extend the
support to lesser implementations.

Let's dissociate the vgic registration from the GIC code and
move it into KVM, where it makes a bit more sense. This also
allows us to mark the gic_kvm_info structures as __initdata.

Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
(cherry picked from commit 0e5cb77706)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I7d20bad2ca51bc6166f1cffa88ac4d53c6dc4ef4
2021-07-13 16:09:12 +01:00
Fuad Tabba
6d9f07d8f1 BACKPORT: arm64: Rename arm64-internal cache maintenance functions
Although naming across the codebase isn't that consistent, it
tends to follow certain patterns. Moreover, the term "flush"
isn't defined in the Arm Architecture reference manual, and might
be interpreted to mean clean, invalidate, or both for a cache.

Rename arm64-internal functions to make the naming internally
consistent, as well as making it consistent with the Arm ARM, by
specifying whether it applies to the instruction, data, or both
caches, whether the operation is a clean, invalidate, or both.
Also specify which point the operation applies to, i.e., to the
point of unification (PoU), coherency (PoC), or persistence
(PoP).

This commit applies the following sed transformation to all files
under arch/arm64:

"s/\b__flush_cache_range\b/caches_clean_inval_pou_macro/g;"\
"s/\b__flush_icache_range\b/caches_clean_inval_pou/g;"\
"s/\binvalidate_icache_range\b/icache_inval_pou/g;"\
"s/\b__flush_dcache_area\b/dcache_clean_inval_poc/g;"\
"s/\b__inval_dcache_area\b/dcache_inval_poc/g;"\
"s/__clean_dcache_area_poc\b/dcache_clean_poc/g;"\
"s/\b__clean_dcache_area_pop\b/dcache_clean_pop/g;"\
"s/\b__clean_dcache_area_pou\b/dcache_clean_pou/g;"\
"s/\b__flush_cache_user_range\b/caches_clean_inval_user_pou/g;"\
"s/\b__flush_icache_all\b/icache_inval_all_pou/g;"

Note that __clean_dcache_area_poc is deliberately missing a word
boundary check at the beginning in order to match the efistub
symbols in image-vars.h.

Also note that, despite its name, __flush_icache_range operates
on both instruction and data caches. The name change here
reflects that.

No functional change intended.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-19-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit fade9c2c6e)
[willdeacon@: Dropped EFI change; fixed conflicts in hibernate.c and
              smp_spin_table.c]
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I219bebf7e6740af1a8d34f68588d32a4497ba957
2021-07-13 16:09:12 +01:00
Fuad Tabba
7cf2172961 UPSTREAM: arm64: Fix cache maintenance function comments
Fix and expand comments for the cache maintenance functions in
cacheflush.h. Adds comments to functions that weren't described
before. Explains what the functions do using Arm Architecture
Reference Manual terminology.

No functional change intended.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-18-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 393239be1b)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Idfae63fb707e8f99783951d4c59a36aedf2eff22
2021-07-13 16:09:12 +01:00
Shaokun Zhang
36c2779402 UPSTREAM: arm64: cacheflush: Remove stale comment
Remove stale comment since commit a7ba121215 ("arm64: use asm-generic/cacheflush.h")

Cc: Christoph Hellwig <hch@lst.de>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Link: https://lore.kernel.org/r/1611575753-36435-1-git-send-email-zhangshaokun@hisilicon.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 1e193c70f5)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I66f250efde64f8c3b65f72c5d6d3016ee847de59
2021-07-13 16:09:12 +01:00
Fuad Tabba
0496899a36 UPSTREAM: arm64: sync_icache_aliases to take end parameter instead of size
To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

No functional change intended.

Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-17-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 8c28d52ccd)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I2fcdf6a802b7b4f8b5679deaee4dd5293aae98ae
2021-07-13 16:09:12 +01:00
Fuad Tabba
f0d833b54e UPSTREAM: arm64: __clean_dcache_area_pou to take end parameter instead of size
To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

No functional change intended.

Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-16-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 406d7d4e2b)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I3054d50460dea012b8e492424fb0d8c1bb4164f8
2021-07-13 16:09:12 +01:00
Fuad Tabba
105159fb94 UPSTREAM: arm64: __clean_dcache_area_pop to take end parameter instead of size
To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

No functional change intended.

Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-15-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit f749448edb)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Idf0290eb348a3bb676f80dedd40b55b8de47e9ce
2021-07-13 16:09:11 +01:00
Fuad Tabba
a1ea39fa1e UPSTREAM: arm64: __clean_dcache_area_poc to take end parameter instead of size
To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

Because the code is shared with __dma_clean_area, it changes the
parameters for that as well. However, __dma_clean_area is local to
cache.S, so no other users are affected.

No functional change intended.

Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-14-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 1f42faf1d2)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I92ac7c3a1dbe3c445ec3dbd059869edfdb2a93f7
2021-07-13 16:09:11 +01:00
Fuad Tabba
39dc6b43cf BACKPORT: arm64: __flush_dcache_area to take end parameter instead of size
To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

No functional change intended.

Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-13-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 814b186079)
[willdeacon@: Dropped EFI change; fixed context conflict in smp_spin_table.c]
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I0a858403b52485341aa96f116bc8d4769f961802
2021-07-13 16:09:11 +01:00
Fuad Tabba
3045a290a9 UPSTREAM: arm64: dcache_by_line_op to take end parameter instead of size
To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

No functional change intended.

Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-12-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 163d3f8069)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I621ea6d3c610a0a0bf8c1641517b5e89a48eba33
2021-07-13 16:09:11 +01:00
Fuad Tabba
65a0f95b16 UPSTREAM: arm64: __inval_dcache_area to take end parameter instead of size
To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

Because the code is shared with __dma_inv_area, it changes the
parameters for that as well. However, __dma_inv_area is local to
cache.S, so no other users are affected.

No functional change intended.

Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-11-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit e3974adb4e)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Ide5024737d08a221f3e7d55caab7e488afd2177c
2021-07-13 16:09:11 +01:00
Fuad Tabba
b53b4c6cdd UPSTREAM: arm64: Fix comments to refer to correct function __flush_icache_range
Many comments refer to the function flush_icache_range, where the
intent is in fact __flush_icache_range. Fix these comments to
refer to the intended function.

That's probably due to commit 3b8c9f1cdf ("arm64: IPI each
CPU after invalidating the I-cache for kernel mappings"), which
renamed flush_icache_range() to __flush_icache_range() and added
a wrapper.

No functional change intended.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-10-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit d044f81418)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I3953e798bc36760eab29677b2ad798cac57c7984
2021-07-13 16:09:11 +01:00
Fuad Tabba
aeb79414b5 UPSTREAM: arm64: Move documentation of dcache_by_line_op
The comment describing the macro dcache_by_line_op is placed
right before the previous macro of the one it describes, which is
a bit confusing. Move it to the macro it describes (dcache_by_line_op).

No functional change intended.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-9-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 06b7a568ca)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I1d9c5bd496234dd3b5da7fef3b41ce01b447a8a5
2021-07-13 16:09:11 +01:00
Fuad Tabba
51f3c766ea UPSTREAM: arm64: assembler: remove user_alt
user_alt isn't being used anymore. It's also simpler and clearer
to directly use alternative_insn and _cond_extable in-line when
needed.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/linux-arm-kernel/20210520125735.GF17233@C02TD0UTHF1T.local/
Signed-off-by: Fuad Tabba <tabba@google.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-8-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 55272ecc3a)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I475d14acf99bb2565440b89a7cc036aa9c2d742f
2021-07-13 16:09:10 +01:00
Fuad Tabba
1104ef908f UPSTREAM: arm64: Downgrade flush_icache_range to invalidate
Since __flush_dcache_area is called right before,
invalidate_icache_range is sufficient in this case.

Rewrite the comment to better explain the rationale behind the
cache maintenance operations used here.

No functional change intended.
Possible performance impact due to invalidating only the icache
rather than invalidating and cleaning both caches.

Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-7-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 5e20e34996)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Id1602829ca1d0b78c689d49cd8c28403e5f5fb63
2021-07-13 16:09:10 +01:00
Pavel Tatashin
bdc7abb880 UPSTREAM: arm64: kexec: move relocation function setup
Currently, kernel relocation function is configured in machine_kexec()
at the time of kexec reboot by using control_code_page.

This operation, however, is more logical to be done during kexec_load,
and thus remove from reboot time. Move, setup of this function to
newly added machine_kexec_post_load().

Because once MMU is enabled, kexec control page will contain more than
relocation kernel, but also vector table, add pointer to the actual
function within this page arch.kern_reloc. Currently, it equals to the
beginning of page, we will add offsets later, when vector table is
added.

Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
Reviewed-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20210125191923.1060122-10-pasha.tatashin@soleen.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 4c3c31230c)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: If8a871fda92bc7f1da9da38622f5de8ea8dcbb93
2021-07-13 16:09:10 +01:00
Pavel Tatashin
a7856033b3 UPSTREAM: arm64: kexec: make dtb_mem always enabled
Currently, dtb_mem is enabled only when CONFIG_KEXEC_FILE is
enabled. This adds ugly ifdefs to c files.

Always enabled dtb_mem, when it is not used, it is NULL.
Change the dtb_mem to phys_addr_t, as it is a physical address.

Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
Reviewed-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20210125191923.1060122-2-pasha.tatashin@soleen.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 117cda9a78)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I3056749ac370558512778bf0370b6137d57368ce
2021-07-13 16:09:10 +01:00
Fuad Tabba
1f0094eecd UPSTREAM: arm64: Do not enable uaccess for invalidate_icache_range
invalidate_icache_range() works on kernel addresses, and doesn't
need uaccess. Remove the code that toggles uaccess_ttbr0_enable,
as well as the code that emits an entry into the exception table
(via the macro invalidate_icache_by_line).

Changes return type of invalidate_icache_range() from int (which
used to indicate a fault) to void, since it doesn't need uaccess
and won't fault. Note that return value was never checked by any
of the callers.

No functional change intended.
Possible performance impact due to the reduced number of
instructions.

Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-6-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 7908072da5)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I543e7f7ca738afd159e059ead95e6480f8d36d6e
2021-07-13 16:09:10 +01:00
Fuad Tabba
5759250f21 UPSTREAM: arm64: Do not enable uaccess for flush_icache_range
__flush_icache_range works on kernel addresses, and doesn't need
uaccess. The existing code is a side-effect of its current
implementation with __flush_cache_user_range fallthrough.

Instead of fallthrough to share the code, use a common macro for
the two where the caller specifies an optional fixup label if
user access is needed. If provided, this label would be used to
generate an extable entry.

Simplify the code to use dcache_by_line_op, instead of
replicating much of its functionality.

No functional change intended.
Possible performance impact due to the reduced number of
instructions.

Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Will Deacon <will@kernel.org>
Reported-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/
Link: https://lore.kernel.org/linux-arm-kernel/20210521121846.GB1040@C02TD0UTHF1T.local/
Signed-off-by: Fuad Tabba <tabba@google.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-5-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 116b7f5594)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: Iaf5b51d5a14f47c0c398025064ee5214a53448b9
2021-07-13 16:09:10 +01:00
Fuad Tabba
299c65460c UPSTREAM: arm64: Apply errata to swsusp_arch_suspend_exit
The Arm errata covered by ARM64_WORKAROUND_CLEAN_CACHE require
that "dc cvau" instructions get promoted to "dc civac".

Reported-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-4-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 46710cf1fc)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: I6cf704d4e323ea625845b23ac5e3e5c849a34b41
2021-07-13 16:09:10 +01:00
Mark Rutland
e496876a30 UPSTREAM: arm64: assembler: add conditional cache fixups
It would be helpful if we could use both `dcache_by_line_op` and
`invalidate_icache_by_line` for user memory without accidentally fixing
up unexpected faults when performing maintenance on kernel addresses.

Let's make this possible by having both macros take an optional fixup
label, and only generating an extable entry if a label is provided.

At the same time, let's clean up the labels used to be globally unique
using \@ as we do for other macros.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Cc: Ard Biesheuvel <aedb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Fuad Tabba <tabba@google.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-3-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit d11b187760)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 192636784
Change-Id: If2f4ea856724039297715d543b598757759636e2
2021-07-13 16:09:09 +01:00