If the hid transfer with size divisible to EPs max packet
size, it needs to set the req->zero to true, then the usb
controller can transfer a zero length packet at the end
according to the USB 2.0 spec.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ia63060b4551d30821beaf494c1ccd7dfb3b6ca22
Set drive-strength for px30, and set drive-strength-s for px30s.
If only drive-strength, that means both for px30 and px30s.
If only drive-strength-s, that means only for px30s.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Idd2437626a28c03624ce0fb41bedf56ec61dabb0
1. switch to normal pll(200M) before disable pd.
2. call pm_runtime_get() to enable pd before change freq(pvtpll).
Change-Id: I8749025c42ec40604361db4d4de2c2b819e0b2a3
Signed-off-by: Liang Chen <cl@rock-chips.com>
Tuing pre-emphasis and turn off differential receiver in suspend mode
for rk3326s and px30s SoCs.
Fix some pc can not recognize the device when using 5m cable, so tuning
usb phy squelch trigger point configure to 100mv for px30s.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: Ida216e8951c1f1dad19fa3ff4c31ede6a53b3458
disable pin_txclkesc inverting.
reset digital logic before select lvds mode.
add support 2.5Gsps lane rate for px30s.
reset digital logic before select TTL mode.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I275d589f56e5963649aee9397eba3a9994e5901d
PX30s has 3bit for drive strength set, the highest bit is from slewrate
bit used on PX30.
Change-Id: I21085cb10247eff9c92979ac24449759b0677b34
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
There are two Temperature Sensor on px30s, channel 0 is for CPU,
channel 1 is for GPU.
set trim for px30s.
Change-Id: I25e16c8d398634d83a3611fa829ee2e9dd974538
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This adds the necessary data for handling efuse on the px30s.
Change-Id: Iaa509d8d22102ff4d054e855d330792f0da8f382
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Fixes:
drivers/mmc/core/mmc.c: In function 'mmc_init_card':
drivers/mmc/core/mmc.c:760:3: warning: 'ecsd' may be used uninitialized in this function [-Wmaybe-uninitialized]
Fixes: bc28e06c42 ("mmc: add thunder boot support")
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I2a82c260f7f03f11bbfdc8a4f341f528ce50d44f
The current ATU setup only supports a single memory resource which
isn't sufficient if there are also prefetchable memory regions. In order
to support multiple memory regions, we need to move away from fixed ATU
slots and rework the assignment. As there's always an ATU entry for
config space, let's assign index 0 to config space. Then we assign
memory resources to index 1 and up. Finally, if we have an I/O region
and slots remaining, we assign the I/O region last. If there aren't
remaining slots, we keep the same config and I/O space sharing.
Link: https://lore.kernel.org/r/20201026181652.418729-1-robh@kernel.org
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Cc: Vidya Sagar <vidyas@nvidia.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I048f7605406a2cd0a4d8eee0c8541011f672756b
(cherry picked from commit 9f9e59a480)
Maybe appear the following case:
-> set gamma
-> config done
-> atomic commit
--> update win format
--> update win address
---> here maybe meet vop hardware frame start, and triggle some config take affect.
---> as only some config take affect, this maybe lead to iommu pagefault.
--> update win size
--> update win other parameters
-> config done
so we add readx_poll_timeout() to make sure the first config done take
effect and then to do next frame config.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I6ec67b374b3afd2bed4a57aa1e7b729964df1736
When the display interface is BT656. the register of
core_dclk_div_sel should always be set 1. Not only 'i'
modes like 480i and 576i, but also 'p' modes like 720p,
both need this setting.
As for BT1120 and other interfaces, this bit should be
1 when display mode belongs to 'i', and 0 when display
mode belongs to 'p'.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: If67614bc5068024d602c6acbbe9676d6245fdf1a
The gem drivers use shmemfs to allocate backing storage for gem objects.
On Samsung Chromebook Plus, the drm/rockchip driver may call
rockchip_gem_get_pages -> drm_gem_get_pages -> shmem_read_mapping_page
to pin a lot of pages, breaking the page reclaim mechanism and causing
oom-killer invocation.
E.g. when the size of a zone is 3.9 GiB, the inactive_ratio is 5. If
active_anon / inactive_anon < 5 and all pages in the inactive_anon lru
are pinned, page reclaim would keep scanning inactive_anon lru without
reclaiming memory. It breaks page reclaim when the rockchip driver only
pins about 1/6 of the anon lru pages.
Mark these pinned pages as unevictable to avoid the premature oom-killer
invocation. See also similar patch on i915 driver [1].
[1]: https://patchwork.freedesktop.org/patch/msgid/20181106132324.17390-1-chris@chris-wilson.co.uk
Change-Id: I67c513481285d3a40cea3bdadbf1f348f00509d6
Signed-off-by: Kuo-Hsin Yang <vovoy@chromium.org>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190108074517.209860-1-vovoy@chromium.org
(cherry picked from commit fb4b49278f)
Once RISC-V snapshot wanna queue raw buffer to DDR until FastAE is
matched, the kernel space should not allow rpm_s/r. Make sure that isp
things won't be changed.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I16335e62ee702b93a1daf526325c3d312ebb0d4b
As we don't do it in resume routine, so in order to be better
compatibale with devices, set it to low.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I0613e05f6d35ba7def7eedd902cfaff73d716952
Fix pin-assignment as per specification.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
Change-Id: Iad7e211e43ebc01607ae534b56666ec56da2f54b
(cherry picked from commit b3e060dc22)
Augmented Power Delivery Objects (A)PDO_s are used by USB-C
PD power adapters to advertize the voltages and currents
they support. There can be up to 7 PDO_s but before PPS
(programmable power supply) there were seldom more than 4
or 5. Recently Samsung released an optional PPS 45 Watt power
adapter (EP-TA485) that has 7 PDO_s. It is for the Galaxy 10+
tablet and charges it quicker than the adapter supplied at
purchase. The EP-TA485 causes an overzealous WARN_ON to soil
the log plus it miscalculates the number of bytes to read.
So this bug has been there for some time but goes
undetected for the majority of USB-C PD power adapters on
the market today that have 6 or less PDO_s. That may soon
change as more USB-C PD adapters with PPS come to market.
Tested on a EP-TA485 and an older Lenovo PN: SA10M13950
USB-C 65 Watt adapter (without PPS and has 4 PDO_s) plus
several other PD power adapters.
Signed-off-by: Douglas Gilbert <dgilbert@interlog.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Cc: stable <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20191230033544.1809-1-dgilbert@interlog.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
(cherry picked from commit c215e48e97)
Change-Id: I51f7e53e6540cdc0ad543f7cbc80416204a1c816
Since the ARGB format was added without processing the address offset
during rotation, the address offset of mmu was calculated incorrectly.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I6bddd21b50bf60cadf493e73cff10c18210c375c
