Let's control the power more be effective.We should make the big clusters
cpu throttle firstly.
Change-Id: I8f055f5856ce0239f9bf8bb5b5f2705b3151ba03
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
we should increase the period cycles to save power since the rk3399 has
the high frequency for tsadc clock.
Change-Id: Ia9481515cac6dd6026d3312ac930329a3e906436
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Whenever the current temperature is updated, the trip points immediately
below and above the current temperature are found. A sensor driver
callback `set_trips' is then called with the temperatures.
Lastly, The sensor will trigger the hardware high temperature interrupts
to increase the sampleing rate and throttle frequency to limit the temperature
rising When performing passive cooling.
Change-Id: I16b2ab4f8fb85425aab5cd3777ca600bd4cace20
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
With interrupt driven thermal zones we pass the lower and upper temperature
on which shall be acted, so in the governor we have to act on the exact lower
temperature to be consistent. Otherwise an interrupt may be generated on the
exact lower temperature, but the bang bang governor does not react.
Change-Id: Ic9dd855b0767d34b15505c1ff12ea99b76cdcea7
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The .get_trend callback in struct thermal_zone_device_ops has the prototype:
int (*get_trend) (struct thermal_zone_device *, int,
enum thermal_trend *);
whereas the .get_trend callback in struct thermal_zone_of_device_ops has:
int (*get_trend)(void *, long *);
Streamline both prototypes and add the trip argument to the OF callback
aswell and use enum thermal_trend * instead of an integer pointer.
While the OF prototype may be the better one, this should be decided at
framework level and not on OF level.
Change-Id: I39c5a38a22c7a2177a35338bc63c8ba36983a7b0
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This adds support for hardware-tracked trip points to the device tree
thermal sensor framework.
The framework supports an arbitrary number of trip points. Whenever
the current temperature is updated, the trip points immediately
below and above the current temperature are found. A .set_trips
callback is then called with the temperatures. If there is no trip
point above or below the current temperature, the passed trip
temperature will be -INT_MAX or INT_MAX respectively. In this callback,
the driver should program the hardware such that it is notified
when either of these trip points are triggered. When a trip point
is triggered, the driver should call `thermal_zone_device_update'
for the respective thermal zone. This will cause the trip points
to be updated again.
If .set_trips is not implemented, the framework behaves as before.
This patch is based on an earlier version from Mikko Perttunen
<mikko.perttunen@kapsi.fi>
Change-Id: I8c33f9859909704583ba8b6632b91ffd58a9628e
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This reverts commit 2f8e5324ef.
Since there are the perfect patches in fromlist to instead of it.
Change-Id: I9f15478d0b0b94805d1bb9539a1cbea42a7af6a1
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
When we use the MIPI screen, the driver will unprepare and disable
the phy_cfg, it will diable its parent pclk_vio:
dw_mipi_dsi_phy_init
--> clk_disable_unprepare
--> clk_disable
--> clk_core_disable(core->parent)
The pclk_vio supply power for pclk_vio_grf, hence, disable pclk_vio_grf will
cause other drivers failed to operate GRF.
Change-Id: I6d5bd27b9478da09209130f1fd5a62c0d4bb1785
Reported-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We now enable HS400 mode for rk3399-evb for rk folks
to do more test for hs400. If any problem, please remove
mmc-hs400-1_8v from rk3399-evb.dtsi and any reports are
welcomed.
Change-Id: If7d9d291351a075fbb258bd04fce2a2f9cb81be3
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This patch assign freq-sel, dr-sel, opdelay to meet the
hw requirement of rk3399-evb.
Change-Id: I1ef98645b5414bcffa0b5711bc9eb63f077a5dc3
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Let's assign clk parent and rate for SCLK_EMMC to meet the
requiremen.
Change-Id: I3730a2124494da51717b1756f488f9df5bcd6423
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
commit 61b914eb81 ("mmc: sdhci-of-arasan: add phy support for
sdhci-of-arasan") introduce phy support for arasan. According to
the vendor's databook, we should make sure the phy is in poweroff
stat before we configure the clk stuff. Otherwise it may cause
some IO sample timing issue from the test. But we don't need this
extra operation while running in non HS200/HS400 mode since phy
doesn't trigger sampling block.
Change-Id: I5506f99e5a3b4d9a4356ad485ceac900c6d754aa
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
According to the databook, 10.2us is the max time for
dll to be ready to work. However from the test, some chips
need 20us for dll to ready. So this patch add some extra
margin for dllrdy to be ready to meet the reality.
Change-Id: Ie5362b4403309d260ac621b8b20a0f5b579d3153
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This patch add some optional configuration for dt. freq-sel can be used
to decide the phy sample clk in order to match the real freq of emmc
controller. dr-sel can be configured to match the requirement of different
drive strength of phy IO. opdelay should be used to adjust the output
delay for clk IO and data IO, which is useful for sloving timing issue.
Change-Id: I0b4da111581c76fbb96b15cd6be653aaa4843c33
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Let's expose the freq-sel, dr-sel, opdalay to dt for user
to decide how to configure their phy.
Change-Id: Ib9ef40b263d3fd669c7bbda666d28c0c55ff6d8e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
We must not to adjust the port order, cause the port id is mapping
to VOP type. Current driver just hardcode that VOP Lit is ID 0, and
VOP Big is ID 1.
ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
if (ret)
val = dp->data->lcdsel_lit | dp->data->lcdsel_mask;
else
val = dp->data->lcdsel_big | dp->data->lcdsel_mask;
Besides eDP could work well with VOP Lit, so we need to revert this
hack. Just revert commit 602f4f79c8.
Change-Id: I69badf2860c83c8211ea23b9f490fd4837dcf22e
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
For RK3999 chip, VOP Big/Lit must configure different display out
mode for eDP controller.
- VOP Lit should output RGB888
- Vop Big should output RGB10
Change-Id: I85bac6c25a990404682483c62a731681d19eca29
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Driver could check the chip type to do some special things.
Change-Id: I2a33da466db0aa5133868c200a122df675f4c925
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The device type would always be ROCKCHIP_DP, so no need to add the
unused devtype check.
Change-Id: I7668a4bdb29700c5397583b9539446f19ae49c3b
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The PLL function was updated to disallow 32KHz in
commit 501f72e9c5 ("ASoC: da7219: Remove support for 32KHz PLL mode"),
but set_dai_sysclk() was missed and still permits it. This patch resolves
that discrepancy.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org kernel/git/broonie/sound.git
topic/da7219 commit fb137ba64a)
Change-Id: I1cf8242745f39ac5ae3cb1aa30989bf4ab8f7f93
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The expected MCLK frequency ranges and the associated dividers
are updated to improve PLL locking in a corner scenario, with low
MCLK frequency near an input divider change boundary.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org kernel/git/broonie/sound.git
topic/da7219 commit 63a450aa4d)
Change-Id: I7b830ef2ea1e25600365872802924f617b6e0274
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
There is a pull up resistor connected to eDP HPD pin on EVB1
hardware, and then eDP controller would always reported that
eDP panel is connected, even if no panel connected.
That would cause driver keep failed on eDP AUX communication,
and lots of annoying error messages would be printed out.
Beside actually the primary panel on EVB1 board is MIPI panel,
few people would have the eDP panel. So let's just disabled
the eDP device on EVB1 board.
Change-Id: Ic2f8b94360821f91e3607c2bfde7d8399fd0080f
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
fb_event would only carry the data number in some special notify action,
other actions wouldn't carry an valid data number, and in this case
kernel would crash, logs like:
[ 4.129846] Unable to handle kernel paging request at virtual address 200000000000
......
[ 4.164618] Hardware name: Rockchip RK3399 Evaluation Board v1 (Chrome OS) (DT)
[ 4.184624] PC is at fb_notifier_callback+0x28/0xac
[ 4.189497] LR is at notifier_call_chain+0x74/0xb4
[ 4.194279] pc : [<ffffffc0005e1468>] lr : [<ffffffc0000b5ba4>] pstate: 20000045
......
[ 5.703780] [<ffffffc0005e1468>] fb_notifier_callback+0x28/0xac
[ 5.709690] [<ffffffc0000b5ba4>] notifier_call_chain+0x74/0xb4
[ 5.715504] [<ffffffc0000b5e70>] __blocking_notifier_call_chain+0x48/0x64
[ 5.722280] [<ffffffc0000b5ea0>] blocking_notifier_call_chain+0x14/0x1c
[ 5.728885] [<ffffffc00036fd98>] fb_notifier_call_chain+0x20/0x28
[ 5.734969] [<ffffffc0003726c0>] register_framebuffer+0x218/0x250
[ 5.741054] [<ffffffc0003b7598>] drm_fb_helper_initial_config+0x2f8/0x374
[ 5.747832] [<ffffffc0003e056c>] rockchip_drm_fbdev_init+0xa8/0xe8
[ 5.754002] [<ffffffc0003dba24>] rockchip_drm_load+0x1e4/0x25c
Change-Id: I3314315a31bbab43489fca85dabc4c6511fc9dee
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
support qos save and restore when power domain on/off.
Change-Id: I5cecf9755467290bc153eeeb75dfd009e7736820
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
commit 074c6a422d)
Rockchip Socs contain quality of service (qos) blocks managing priority,
bandwidth, etc of the connection of each domain to the interconnect.
These blocks loose state when their domain gets disabled and therefore
need to be saved when disabling and restored when enabling a power-domain.
These qos blocks also are similar over all currently available Rockchip
SoCs.
Change-Id: I03c80e01ae0fd1a66a67db15f24869047862f13f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
commit 71daabca34)
Check return value of syscon_node_to_regmap for
rockchip_pm_domain_probe. If err value is returned, probe
procedure should abort.
Change-Id: I8b6f2a62d383c5cae5b69e030a8a8e2ad9cc18c1
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
commit 4506697d9f)
Gpu's 480MHz need to select usbphy_480m as parent.
The jitter will be lower, if sclk_wifidsp is supplied by pll_wifi.
Change-Id: I13e5077d55ab80e5224bac36b469e39d556bd347
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
When changing the clock-rate, currently a new parent is set first and a
divider adapted thereafter. This may result in the clock-rate overflowing
its target rate for a short time if the new parent has a higher rate than
the old parent.
While this often doesn't produce negative effects, it can affect components
in a voltage-scaling environment, like the GPU on the rk3399 socs, where
the voltage than simply is to low for the temporarily to high clock rate.
For general clock hirarchies this may need more extensive adaptions to
the common clock-framework, but at least for composite clocks having
both parent and rate settings it is easy to create a short-term solution to
make sure the clock-rate does not overflow the target.
Change-Id: Iceb40b24ef13db6947be3d797ea90b3e1055b9df
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org clk/linux.git clk-next
commit 9e52cec04f)
We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.
Fix the newly added rk3399 clock code to respect that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org kernel/git/mmind/linux-rockchip.git
v4.7-clk/next commit 995d3fdeb2)
Conflicts:
drivers/clk/rockchip/clk-rk3399.c
[
zx: this patch is based on the old version by Heiko on the upstream:
commit de4939f7fc
Author: Xing Zheng <zhengxing@rock-chips.com>
Date: Fri Mar 25 19:33:48 2016 +0800
clk: rockchip: rk3399: add some aclk/dclk IDs for vop0/vop1
]
Change-Id: I6aeda93a54ab96ab885f9bf04a5f21b07d1c9a89
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
