[Why]
DML Initialization was previously done on dcn21_resource initialization.
This meant that DML soc struct was populated with hardcoded values.
[How]
Move DML initialization to after updating bounding box, to use clock table
values from SMU.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
PHY will sometimes be in bad state on hotplugging display from USB-C
dongle.
[How]
Add additional calls to disable and then enable PHY before link training
starts during verify_link_cap.
Signed-off-by: George Shen <george.shen@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Recent double buffering changes for dcn2 use IX_REG_READ.
However, this macro returns the full register value, with the need to
manually shift and mask it to retrieve field data.
[How]
Create new IX_REG_GET macro that handles shift and mask.
Use this for double buffering reads instead of IX_REG_READ.
Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
When rapidly adjusting color temperature, screen tearing was observed.
This was due to overwritten values in gamut remap registers.
This issue was solved for OCSC and ICSC by alternating between "A" and
"B" registers to double buffer the writes.
[How]
Create new set_gamut_remap and program_gamut_remap for dcn20.
Alternate which registers are written to by switching modes each time.
Also fixes ICSC mode reg read to use proper data offset.
Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
When rapidly adjusting video brightness, screen tearing was observed.
This was due to overwritten values in ICSC registers. In dcn10, this issue had been
fixed by implementing double buffering via alternating ICSC modes.
However, the second register set used in dcn1 doesn't exist in dcn2.
[How]
Create new program_input_csc for dcn20.
Use ICSC_B registers instead of COMA registers as second set.
Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Don't want to start HW discovery unless we have lost power,
as doing rediscovery otherwise is both unnecessary and time consuming.
Before this change it takes 40 seconds to go in to suspend, after it
takes 27 seconds
[How]
Accelerated mode gets cleared if we lose power. Only do detection if
this register is cleared
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
48mhz turn off feature does not work on HDMI and DVI, but the feauture
was only blocked on HDMI, this change will apply the same wa on DVI
[HOW]
Apply workaround for all TMDS signal types (HDMI, DVI single/dual link)
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
When rapidly adjusting colour properties (e.g. brightness), screen tearing was observed.
This was due to overwritten values in OCSC registers. In dcn10, this issue had been fixed by
implementing double buffering by alternating OCSC modes.
[How]
Alternate which OCSC registers are used by switching modes each time.
This double buffers the CSC writes.
Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
We need to ensure that the DMUIF in MMHUBBUB is also in reset so we
aren't generating requests while the DMCUB is in reset.
[How]
Set DMUIF_SOFT_RESET=1 on reset and DMUIF_SOFT_RESET=0 on reset
release.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
i.MX defconfig update for 5.6:
- Enable i.MX8MP clock driver in arm64 defconfig.
- Enable Crypto CAAM driver support as module in arm64 defconfig.
- Enable ILI210X touch driver, USB CDC ACM function, NFS_V4 support and
TFP410 DVI bridge driver support in arm32 imx_v6_v7_defconfig.
* tag 'imx-defconfig-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: defconfig: Enable CONFIG_CLK_IMX8MP by default
arm64: defconfig: Enable CRYPTO_DEV_FSL_CAAM
ARM: imx_v6_v7_defconfig: Select the TFP410 driver
ARM: imx_v6_v7_defconfig: Enable NFS_V4_1 and NFS_V4_2 support
ARM: configs: imx_v6_v7_defconfig: enable USB ACM
ARM: imx_v6_v7_defconfig: Enable TOUCHSCREEN_ILI210X
Link: https://lore.kernel.org/r/20200113034006.17430-6-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
i.MX arm64 device tree update for 5.6:
- New board support: i.MX8MQ based Thor96 board, Google i.MX8MQ Phanbell
board, LX2160A based Solidrun Clearfog CX and Honeycomb boards.
- Add eLCDIF controller and missing SAI nodes for i.MX8MQ SoC.
- Add Crypto CAAM support for i.MX8MM and i.MX8MN.
- Drop unneeded "simple-bus" from anatop node on i.MX8MM and i.MX8MN.
- Drop unused/undocumented "fsl,aips-bus" and "fsl,imx8mq-aips-bus"
compatibles from i.MX8M SoCs.
- Add DDR controller nodes for i.MX8M devices.
- Add EEPROM description for imx8mq-hummingboard-pulse and
imx8mq-sr-som boards.
- Enable USB1 and TypeC support for imx8mn-evk board.
- Add FlexSPI and QSPI support for a few Layerscape SoCs and boards.
- Add External MDIO1 node and the two RGMII PHYs connected on LX2160A.
- Add missing SAI devices and set SAIs into async mode on LS1028A.
- Other random device additions and enhancement for various platforms.
* tag 'imx-dt64-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (35 commits)
arm64: dts: imx8mn: Memory node should be in board DT
arm64: dts: imx8mm: Memory node should be in board DT
arm64: dts: imx8mn: add crypto node
arm64: dts: imx8mq-hummingboard-pulse: add eeprom description
arm64: dts: imx8mq-sr-som: add eeprom description
arm64: dts: ls208xa: Update qspi node properties for LS2088ARDB
arm64: dts: freescale: Add devicetree support for Thor96 board
arm64: dts: imx8mq-librem5-devkit: add accelerometer and gyro sensor
arm64: dts: imx8mm: Add Crypto CAAM support
arm64: dts: freescale: add initial support for Google i.MX 8MQ Phanbell
arm64: dts: ls1028a-rdb: enable emmc hs400 mode
arm64: dts: ls1028a: Update edma compatible to fit eDMA driver
arm64: dts: imx8m: drop "fsl,aips-bus" and "fsl,imx8mq-aips-bus"
arm64: dts: imx8mm: Add missing mux options for UART1 and UART2 signals
arm64: dts: lx2160a: add dts for CEX7 platforms
arm64: dts: lx2160a: add emdio2 node
arm64: dts: ls1028a: put SAIs into async mode
arm64: dts: ls1028a: add missing sai nodes
arm64: dts: imx8mn-evk: enable usb1 and typec support
arm64: dts: imx8mn: Remove setting for IMX8MN_CLK_USB_CORE_REF
...
Link: https://lore.kernel.org/r/20200113034006.17430-5-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
i.MX device tree update for 5.6:
- New board support: i.MX6SL based Tolino Shine 3 eBook reader,
i.MX7ULP Embedded Artists COM Board, i.MX6Q/DL based Gateworks
Ventana Boards.
- A couple of series from Andrey Smirnov to enhance i.MX6 RDU2 and
VF610 ZII boards.
- Add revision in board compatible string for imx6sx-sdb-reva and
imx7d-sdb-reva board.
- A fixup on imx6sl-tolino-shine3 board to remove incorrect power
supply assignment.
- Set initial buck regulator modes explicitly for phycore-imx6 board,
so that a wrong initial mode set by bootloader does not interfere.
- Add Add LCD support for imx7d-pico board.
- A couple of patches from Michael Grzeschik to enhance USB Host
support on i.MX25.
- A couple of patches from Michael Trimarchi to remove duplicate
Ethernet PHY reset properties on imx6qdl-icore and switch to
phy-handle.
- A couple of changes to add extirq node support on LS1021A SoC and
make use of it on the LS1021A-TSN board.
- A few random device additions and improvements on various boards.
* tag 'imx-dt-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (33 commits)
ARM: dts: imx: Add GW5912 board support
ARM: dts: imx: Add GW5913 board support
ARM: dts: imx: Add GW5910 board support
ARM: dts: imx: Add GW5907 board support
ARM: dts: imx6ul-14x14-evk: Pass the "broken-cd" property
ARM: dts: imx6sl-tolino-shine3: Remove incorrect power supply assignment
ARM: dts: imx7d-pico: Add LCD support
ARM: dts: imx6qdl-icore: Add fec phy-handle
ARM: dts: imx6qdl-icore-1.5: Remove duplicate phy reset methods
ARM: dts: imx7: Unify temp-grade and speed-grade nodes
ARM: dts: imx6: phycore-som: add pmic onkey device
ARM: dts: imx51-babbage: Fix the DVI output description
ARM: dts: imx6qdl-apalis: mux HDMI CEC pin
ARM: dts: imx6sll: add PXP module
ARM: dts: colibri-imx6ull: correct wrong pinmuxing and add comments
ARM: dts: vf610-zii-scu4-aib: Add node for switch watchdog
ARM: dts: vf610-zii-scu4-aib: Use generic names for DT nodes
ARM: dts: vf610-zii-dev-rev-b: Drop redundant I2C properties
ARM: dts: phycore-imx6: set buck regulator modes explicitly
ARM: dts: imx6: rdu2: Limit USBH1 to Full Speed
...
Link: https://lore.kernel.org/r/20200113034006.17430-4-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
i.MX SoC changes for 5.6:
- Add support for reading serial number from OCOTP on i.MX7ULP.
- A patch from Anson to enable ARM_ERRATA_814220 for i.MX6UL & i.MX7D,
and a fixup patch from Arnd to select the option only for ARMv7-A.
* tag 'imx-soc-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: only select ARM_ERRATA_814220 for ARMv7-A
ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D
ARM: imx: Add i.MX7ULP SoC serial number support
ARM: imx: Fix boot crash if ocotp is not found
ARM: imx_v6_v7_defconfig: Explicitly restore CONFIG_DEBUG_FS
ARM: dts: imx6ul-evk: Fix peripheral regulator
arm64: dts: ls1028a: fix reboot node
arm64: dts: ls1028a: fix typo in TMU calibration data
ARM: imx: Correct ocotp id for serial number support of i.MX6ULL/ULZ SoCs
ARM: dts: e60k02: fix power button
ARM: dts: imx6ul: imx6ul-14x14-evk.dtsi: Fix SPI NOR probing
Link: https://lore.kernel.org/r/20200113034006.17430-2-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
i.MX driver changes for 5.6:
- Add i.MX8MP SoC driver support.
- Allow IMX DSP Protocol driver to be built as module.
- Add COMPILE_TEST for IMX_SCU_SOC driver to increase build coverage.
- Print SoC type and revision in i.MX8 SoC driver, as this is useful
information to have when looking through boot log.
* tag 'imx-driver-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
firmware: imx: Allow IMX DSP to be selected as module
soc: imx: Enable compile testing of IMX_SCU_SOC
soc: imx: Add i.MX8MP SoC driver support
soc: imx8: print SoC type and revision
Link: https://lore.kernel.org/r/20200113034006.17430-1-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
[Why]
The inst firmware isn't necessarily fully flushed to framebuffer
memory and the DMCUB can hang due to invalid inst being parsed.
[How]
Like the fix to flush ringbuffer commands before updating the inbox
write pointer we need to read back inst memory before writing the
CW0 registers.
Add a helper to read 64-byte chunks to avoid a large temporary buffer.
Read the remaining leftover bytes if the inst_fb isn't fully aligned.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
mvebu drivers for 5.6 (part 1)
- Various cleanup on the following drivers:
- Turris Mox rWTM firmware
- Moxtet bus
- Armada 37xx rWTM mailbox
- Marvell EBU Device Bus
* tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu:
mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resource
memory: mvebu-devbus: convert to devm_platform_ioremap_resource
bus: moxtet: declare moxtet_bus_type as static
firmware: turris-mox-rwtm: small white space cleanup
Link: https://lore.kernel.org/r/877e1x3nxc.fsf@FE-laptop
Signed-off-by: Olof Johansson <olof@lixom.net>
arm64: tegra: Default configuration updates for v5.6-rc1
This enables the USB GPIO connector and Tegra XUDC drivers in the
default configuration.
* tag 'tegra-for-5.6-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: defconfig: Enable tegra XUDC support
Link: https://lore.kernel.org/r/20200111005526.2413959-1-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
arm64: tegra: Device tree changes for v5.6-rc1
These patches do some cleanup to existing nodes, add the memory
subsystem on Tegra186 and Tegra194 as well as the FUSE and APB MISC
nodes on Tegra194. There are also a few additions to the Jetson Nano
device tree to enable additional features and the force recovery
button on the Jetson AGX Xavier now produces a key code that is
actually valid. Finally, an alias is added for the Ethernet card on
Jetson TX2 to allow firmware to find it and pass a MAC address via
device tree.
* tag 'tegra-for-5.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Allow bootloader to configure Ethernet MAC on Jetson TX2
arm64: tegra: Redefine force recovery key on Jetson AGX Xavier
arm64: tegra: Enable SDIO on Jetson Nano M.2 Key E
arm64: tegra: Enable PWM fan on Jetson Nano
arm64: tegra: Add fuse/apbmisc node on Tegra194
arm64: tegra: Make XUSB node consistent with the rest
arm64: tegra: Add the memory subsystem on Tegra194
arm64: tegra: Add external memory controller on Tegra186
arm64: tegra: Add interrupt for memory controller on Tegra186
arm64: tegra: Rename EMC on Tegra132
arm64: tegra: Let the EMC hardware use the EMC clock
Link: https://lore.kernel.org/r/20200111003553.2411874-7-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
ARM: tegra: Device tree changes for v5.6-rc1
This adds memory timings for the PAZ100 and does some minor cleanup for
the external memory controller device tree node on Tegra124.
* tag 'tegra-for-5.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: dts: tegra20: paz00: Add memory timings
ARM: tegra: Rename EMC on Tegra124
ARM: tegra: Let the EMC hardware use the EMC clock
Link: https://lore.kernel.org/r/20200111003553.2411874-6-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
ARM: tegra: Core changes for v5.6-rc1
Contains a couple of fixes for RAM repair on Tegra124.
* tag 'tegra-for-5.6-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Use clk_m CPU on Tegra124 LP1 resume
ARM: tegra: Modify reshift divider during LP1
ARM: tegra: Enable PLLP bypass during Tegra124 LP1
Link: https://lore.kernel.org/r/20200111003553.2411874-5-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
soc: tegra: Changes for v5.6-rc1
This adds a couple of optimizations to how the chip ID and straps are
read and adds support for the FUSE block on Tegra194. Included is also a
small optimization for the coupled regulator driver to abort early if no
voltage change has occurred.
* tag 'tegra-for-5.6-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: fuse: Unmap registers once they are not needed anymore
soc/tegra: fuse: Correct straps' address for older Tegra124 device trees
soc/tegra: fuse: Warn if straps are not ready
soc/tegra: fuse: Cache values of straps and Chip ID registers
soc/tegra: regulators: Do nothing if voltage is unchanged
soc/tegra: fuse: Add APB DMA dependency for Tegra20
soc/tegra: fuse: Add Tegra194 support
Link: https://lore.kernel.org/r/20200111003553.2411874-4-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
[Why]
There's a data race that can occur between when we update the
inbox write pointer vs when the memory for the command actually gets
flushed from the map to the framebuffer.
DMCUB can read stale or partially invalid data when this race occurs.
[How]
Before updating the write pointer we can read back all pending commands
to ensure that we stall for the writes to be flushed to framebuffer.
We don't need to worry about choosing HDP vs VM flush with this
mechanism.
Drop the dmub_srv_cmd_submit() while we're updating this to work
correctly since nothing was actually using this API and the caller
should be explicit about the API flow here - by doing this on execute
we can give some extra time for the flush to finish while
preparing other commands.
We should try to avoid writing single commands
because of this overhead.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
If the specific monitor supports DSC, the secondary link should be
disabled, and the other way around, too: if either that monitor or
our ASIC doesn't support DSC, the secodary link should be enabled.
[how]
Add a monitor patch and disable secondary link if that monitor
is detected and if ASIC supports DSC, or otherwise enable secondary
link.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
memory: tegra: Changes for v5.6-rc1
This adds a couple of fixes for the Tegra30 EMC frequency scaling code
and adds support for EMC frequency scaling on Tegra186 and later.
* tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
memory: tegra30-emc: Correct error message for timed out auto calibration
memory: tegra30-emc: Firm up hardware programming sequence
memory: tegra30-emc: Firm up suspend/resume sequence
memory: tegra: Correct reset value of xusb_hostr
memory: tegra: Add support for the Tegra194 memory controller
memory: tegra: Only include support for enabled SoCs
memory: tegra: Support DVFS on Tegra186 and later
memory: tegra: Add system sleep support
memory: tegra: Extract memory client SID programming
memory: tegra: Add per-SoC data for Tegra186
memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186
memory: tegra: Implement EMC debugfs interface on Tegra30
memory: tegra: Implement EMC debugfs interface on Tegra20
memory: tegra: Refashion EMC debugfs interface on Tegra124
Link: https://lore.kernel.org/r/20200111003553.2411874-3-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
[Why]
Previous implementation we may have residual chroma address offset
if transition from wa enable -> wa disable.
[How]
Clear address offset cache when viewport updates. Also update the
vp size check condition to account for rotation angle
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Upon exiting a fixed active VRR state, the state isn't cleared. This
leads to the variable VRR range to be calculated incorrectly.
[how]
Set fixed active state to false when updating vrr params
Signed-off-by: Amanda Liu <amanda.liu@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
To allow the flexibilty for user to disable gpu recovery
in RAS recovery path by module parameter amdgpu_gpu_recovery
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
bus: tegra: Changes for v5.6-rc1
Contains a single fix to remove a Kconfig dependency that's no longer
required.
* tag 'tegra-for-5.6-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
bus: tegra-aconnect: Remove PM_CLK dependency
Link: https://lore.kernel.org/r/20200111003553.2411874-2-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
dt-bindings: Changes for v5.6-rc1
This contains a conversion of the Tegra124 EMC bindings to json-schema
as well as the addition of the bindings for the memory subsystem found
on Tegra186 and Tegra194.
* tag 'tegra-for-5.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: memory: Add Tegra186 memory subsystem
dt-bindings: memory: Add Tegra194 memory controller header
dt-bindings: memory: Add Tegra186 memory client IDs
dt-bindings: memory-controller: Convert Tegra124 EMC to json-schema
Link: https://lore.kernel.org/r/20200111003553.2411874-1-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
