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Author SHA1 Message Date
Finley Xiao
98a9b2cbb4 MALI: bifrost: Add memory regulator support 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I95d3ceccc5cd14caefb96c1c3266d7b4d8520719
 2021-11-23 16:34:03 +08:00
Caesar Wang
2084b9f118 MALI: bifrost: fixes wrong number of regulators 
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Icb1e4a388e6e8720036b6a1d85a13b5e2491cf4d
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
 2021-11-23 16:32:28 +08:00
Sugar Zhang
7785ff2166 arm64: dts: rockchip: rk3588: Assign clk parent for DAIs 
This patch assigns PLL_AUPLL as the parent of digital audio
interface default.

Except for:
 I2S1_8CH which is fixed bind to PLL_CPLL
 PDM0 which is fixed 300M/200M from PLL_GPLL/CPLL.

And Set PLL_AUPLL to 786.432M(48k group) default to achieve
better jitter performance.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I1f06a7a37691803b41768ac329917912c377a9e7
 2021-11-23 15:37:15 +08:00
Sugar Zhang
f9bd0486a1 clk: rockchip: rk3588: Add audio fracpll freq 
This patch adds more audio fracpll freq around 800M.

786432000 for SR:
  8k, 16k, 24k, 48k, 96k, 192k

722534400 for SR:
  11.025k 22.05k, 44.1k, 88.2k, 176.4k

According to CRU Chapter:

+------------+---------------------------------------------------------+
| PLL Type   | Equation                                                |
+------------+---------------------------------------------------------+
| FRACPLL    | FFVCO = ((m + k / 65536) * FFIN) / p                    |
|            | FFOUT = FFVCO / 2^s                                     |
+------------+---------------------------------------------------------+

e.g. to achieve PLL rate: 786432000

step1:

equation: FFVCO = FFOUT * 2^s to get VCO as much higher as possible in
ranges for better jitter performance.

FFVCO = 786432000 * 2^2 = 3145728000

step2:

equation: ref = FFIN / P, (m + k / 65536) = FFVCO / ref
ref should be as much higher as possible for better jitter performance.

we can try to iterate from high freq to low to find the best parameter.

step3:

the final FFOUT should be measured by devices, sush as frequency
counter.

RK3588_PLL_RATE(786432000, 2, 262, 2, 9437)
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850)

+------------------------------------------------------------------------+
| MHz  | 1~63 | 64~1024 | 0~6 | 0~65535 |     |  2250~4500  |  36~4500   |
+------------------------------------------------------------------------+
| FFIN |  p   |    m    |  s  |    k    | ref |    FFVCO    |   FFOUT    |
+------------------------------------------------------------------------+
| 24   |  2   |   262   |  2  |   9437  | 12  | 3145.727993 | 786.431998 |
+------------------------------------------------------------------------+
| 24   |  8   |   963   |  2  |  24850  |  3  | 2890.137560 | 722.534390 |
+------------------------------------------------------------------------+

Target freq measured by KEYSIGHT-53220A (Universal Frequency Counter)

+------------+---------------------+---------------------+-------------+
| PLL (MHz)  | Freq required (MHz) | Freq measured (MHz) | Delta (ppm) |
+------------+---------------------+---------------------+-------------+
| 786.432000 | 49.152000           | 49.151360           | 13          |
+------------+---------------------+---------------------+-------------+
| 786.432000 | 12.288000           | 12.287841           | 13          |
+------------+---------------------+---------------------+-------------+
| 722.534400 | 45.158400           | 45.157816           | 13          |
+------------+---------------------+---------------------+-------------+
| 722.534400 | 11.289600           | 11.289453           | 13          |
+------------+---------------------+---------------------+-------------+

And this patch also fix freq for 983.04M and 903.168M.

Before:

RK3588_PLL_RATE(983040000, 3, 491, 2, 34078)
RK3588_PLL_RATE(903168000, 3, 451, 2, 38272)

+------------+---------------------+---------------------+-------------+
| PLL (MHz)  | Freq required (MHz) | Freq measured (MHz) | Delta (ppm) |
+------------+---------------------+---------------------+-------------+
| 983.040000 | 49.152000           | 49.051368           | 2047        |
+------------+---------------------+---------------------+-------------+
| 983.040000 | 12.288000           | 12.262841           | 2047        |
+------------+---------------------+---------------------+-------------+
| 903.168000 | 45.158400           | 45.057819           | 2227        |
+------------+---------------------+---------------------+-------------+
| 903.168000 | 11.289600           | 11.264454           | 2227        |
+------------+---------------------+---------------------+-------------+

After:

RK3588_PLL_RATE(983040000, 4, 655, 2, 23592)
RK3588_PLL_RATE(903168000, 6, 903, 2, 11009)

+------------+---------------------+---------------------+-------------+
| PLL (MHz)  | Freq required (MHz) | Freq measured (MHz) | Delta (ppm) |
+------------+---------------------+---------------------+-------------+
| 983.040000 | 49.152000           | 49.151367           | 13          |
+------------+---------------------+---------------------+-------------+
| 983.040000 | 12.288000           | 12.287841           | 13          |
+------------+---------------------+---------------------+-------------+
| 903.168000 | 45.158400           | 45.157818           | 13          |
+------------+---------------------+---------------------+-------------+
| 903.168000 | 11.289600           | 11.289454           | 13          |
+------------+---------------------+---------------------+-------------+

Fixes: 72c304699f ("clk: rockchip: rk3588: Add audio fracpll freq")

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iacc74d135efacef5b6b65d30bdf235ceec0fe970
 2021-11-23 15:37:09 +08:00
Shunhua Lan
267e9b4290 ASoC: es7202: add supply voltage recognizing and set channels_max to 8 
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: Icda031758b217c1b7c3524d6fe9ffd6a542f8bcf
 2021-11-23 15:15:08 +08:00
Sandy Huang
0e6433e98f drm/rockchip: vop2: add support RGB101010 and update dither config 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I616225d36ff3a7385c5937fc663ff063f0683b0c
 2021-11-23 15:10:27 +08:00
Elaine Zhang
cb1f0723c1 clk: rockchip: rk3588: use COMPOSITE_DCLK for dclk_vp2 
div = DIV_ROUND_UP_ULL(400000000, rate);

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I6106b9e661db21392af3185c4d3a1f17cd5d844f
 2021-11-23 11:20:24 +08:00
shengfei Xu
7534ec9a51 arm64: dts: rockchip: rk806: bind the rk806 to the rk3588 
rename "rk806-double.dtsi" to "rk3588-rk806-daul.dtsi"
rename "rk806-single.dtsi" to "rk3588-rk806-single.dtsi"

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I0f2de1d32a0cd2ed6d551dca7cdf7ebb6eb6d990
 2021-11-23 11:09:30 +08:00
Tao Huang
bb61e2f640 arm64: rockchip_gki.config: Enable CONFIG_SND_SOC_ROCKCHIP_HDMI 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ifabffd2a06c9ba94766dc7c6f236b395c0754323
 2021-11-23 10:44:59 +08:00
XiaoTan Luo
7579511593 arm64: configs: rockchip_defconfig: enable SND_SOC_ROCKCHIP_HDMI 
enable ROCKCHIP_HDMI ASoC driver to report jack status.

Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I180161b64878c34bda0e5b7bd354cc993d8abee9
 2021-11-23 10:43:12 +08:00
XiaoTan Luo
e03ac60bd0 ASoC: rockchip: add machine driver for hdmi audio 
this patch is used for rockchip HDMI audio output.

Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I577179e7563ad241014d023da12af1e622e84c9a
 2021-11-23 10:43:12 +08:00
shengfei Xu
5a55442ff1 regulator: rk806: support shutdown/reset function 
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I3fecda310463dd183bb85adc0671f356ff81cd1a
 2021-11-23 10:28:51 +08:00
Tao Huang
439876311b video/rockchip: rga2: depends on !ROCKCHIP_MULTI_RGA 
prevent select RGA2 and MULTI_RGA both.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I822dc6bed24cae7c86135cf1b4af0cfc6e681240
 2021-11-23 09:45:34 +08:00
Lin Jinhan
df3b2a9643 crypto: rockchip: core: modify buffer addr_vir size to 8 PAGES 
Increase the buffer size from 1 to 8 pages. Data can be copied to
 the buffer for hardware crypto calculation when the scatter list
 does not meet the alignment requirement and data length less than
 8 pages.

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: Id5e36f4fa7fc042ea4d117071ae9fee16ebb3494
 2021-11-22 21:27:39 +08:00
Lin Jinhan
6ad785b40f crypto: rockchip: v1&v2: switch ablkcipher to skcipher API 
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I2936c26d1a9600ecbdb86ab2821a502371e9c2bc
 2021-11-22 21:24:44 +08:00
Damon Ding
3a84f255cd arm64: dts: rockchip: rk3588: add support for BT656 
add dts file:
	rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dts

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I82e7bf46ed0c6c0a3a35c9528a026d24bf2cfc43
 2021-11-22 21:19:12 +08:00
Damon Ding
48801131ab arm64: dts: rockchip: rk3588: add support for BT1120 
add dts file:
	rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I985b763ccaecc6aa94010da92bbad962b1562a45
 2021-11-22 21:17:23 +08:00
Damon Ding
1ed78e4f4e arm64: dts: rockchip: rk3588: add pinctrl of bt656 mode 
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ia659d2b486aa31fd36fc04c971620894e9db1d7e
 2021-11-22 21:16:22 +08:00
Tao Huang
749c4a0479 arm64: rockchip_defconfig: Remove CONFIG_TYPEC 
Remove CONFIG_TYPEC which is selected by CONFIG_PHY_ROCKCHIP_USBDP.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I50cc3b7dd9659372fc46d4cb1bfea18fea3cca0c
 2021-11-22 20:17:56 +08:00
Alex Zhao
23daad7340 arm64: dts: rockchip: add WIFI/BT/Ethernet for rk3588 evb3 
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: Iae3395967ba0a71724fa959c1f3a1085927a130e
 2021-11-22 20:14:04 +08:00
Tao Huang
a8c903523a arm64: rockchip_gki.config: Enable CONFIG_ROCKCHIP_MULTI_RGA 
-CONFIG_ROCKCHIP_RGA2=m

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I4ba3733fbcc1af0166208eb686b62df029959daf
 2021-11-22 19:58:14 +08:00
Tao Huang
b9f76e7405 arm64: rockchip_gki.config: Enable CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ic862bc1839830e3b0f6c9b22c009e8534e5e53b2
 2021-11-22 19:52:06 +08:00
Kever Yang
e5dba42181 arm64: dts: rockchip: rk3588-evb4: Enable power for clk buffer chip 
rk3588 has two pcie3.0 phy which need two way reference clock, and the
PCIe slot only have one way clock input, so it need a clock buffer chip
to output two way clock to rk3588. Enable the power when it's boot on.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: Ie65323ecd2a2e210d95405cce4db1a37c2113f51
 2021-11-22 18:55:20 +08:00
Tao Huang
d7dc349edc arm64: rockchip_gki.config: Enable CONFIG_AP6XXX and CONFIG_WL_ROCKCHIP 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I5ea4991a5376bffbaf53f930b501bbcb0358fc45
 2021-11-22 18:29:29 +08:00
Tao Huang
57ba9810b3 arm64: rockchip_gki.config: Enable CONFIG_ROCKCHIP_DW_DP 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I50d9da5839b161e13528e0040a218d9c59bc8124
 2021-11-22 18:16:18 +08:00
Tao Huang
8e6c4c23bc arm64: rockchip_gki.config: Enable CONFIG_ARM_SMMU_V3 
There are two MMU600 instances in RK3588.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I63242fc5ed001c3c46956e8ce5695b7c33350e9b
 2021-11-22 17:56:20 +08:00
Tao Huang
7ce7cb6b20 include/uapi/linux/rk_vcm_head.h: do not leak CONFIG_COMPAT to userspace 
error: include/uapi/linux/rk_vcm_head.h: leak CONFIG_COMPAT to user-space

Fixes: 3c60ce2725 ("media: move rk_vcm_head.h from drivers/media/i2c/ to include/uapi/linux/")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I64a4ef35c25fd11997689575059ae0b7ee90369a
 2021-11-22 17:43:53 +08:00
Shawn Lin
ebe7656936 mmc: sdhci-of-dwcmshc: Add more clk management for runtime PM 
core clk should be alive for DLL to work properlly, but we can
set it to 24MHz to save power. And other bulk clks can be closed
too.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I402ae1e8ca8cd00f33e8bbdeaa89e41546f954ff
 2021-11-22 17:34:34 +08:00
Liang Chen
0cc6d6bfb2 arm64: dts: rockchip: rk3588: delete RK3588_PD_NVM 
RK3588_PD_NVM need keep always on for emmc.

Change-Id: Ia96894eb4bf640799893c3ae68ac68ed15ea989d
Signed-off-by: Liang Chen <cl@rock-chips.com>
 2021-11-22 17:24:14 +08:00
Li Huang
8ca0b5936e video/rockchip: rga3: Init version 1.1.1 
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Change-Id: Ib19d2d141e6b0eefa9d67b062e564559f58fb0b4
 2021-11-22 17:18:58 +08:00
Li Huang
cae208fa6f arm64: dts: rockchip: rk3588-nvr.dtsi: Enable rga node 
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Change-Id: Ieb2850dd5cab6a1bf23278c6cf434610434d49b3
 2021-11-22 17:18:58 +08:00
Li Huang
85f8bf3ea3 arm64: dts: rockchip: rk3588-evb.dtsi: Enable rga node 
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Change-Id: I33021a89e5f7206168600cae44210d361b348f4a
 2021-11-22 17:18:58 +08:00
Li Huang
282ab28b4a arm64: dts: rockchip: rk3588: Add multicore rga node 
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Change-Id: If1b2198132bfd53aff65d483381ee7d63d5d727f
 2021-11-22 17:18:58 +08:00
Li Huang
df9e86a527 arm64: rockchip_defconfig: Enable CONFIG_ROCKCHIP_MULTI_RGA 
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Change-Id: I95fbef30eb87fc69379cfce7feb976bfc261ab8c
 2021-11-22 17:18:58 +08:00
Li Huang
9a683ef131 arm64: rockchip_linux_defconfig: Enable CONFIG_ROCKCHIP_MULTI_RGA 
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Change-Id: I59ee04e134f22131acd697c532c2a62ae53d27c2
 2021-11-22 17:18:58 +08:00
Wyon Bi
c2cce53ab0 drm/rockchip: dw-dp: Add support for split mode 
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I707d1a84d232562338b2676a7037dc0d6ec49be4
 2021-11-22 17:07:39 +08:00
Wyon Bi
3cc26c4bbc drm/rockchip: drv: Add helper function drm_mode_convert_to_{split,origin}_mode() 
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I1a40d0d296c5e82cc5d40378af002132d9949e04
 2021-11-22 17:07:39 +08:00
Wang Jie
7cba838b19 arm64: dts: rockchip: rk3588s-tablet: configure sink pdos 
Configure the supported voltage/current list in the
tablet as a sink to realize PD fast charging.

The maximum charging voltage and current depend on
the charger ic and rk3588s tablet. Taking into
account the stable operation of the tablet, the
software is limited to a maximum voltage of 12v
and a maximum current of 3A.

Change-Id: I5c707e58434ecbe477a650beb7211535ca7c83d4
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
 2021-11-22 16:57:47 +08:00
Wang Jie
0da78695ed arm64: dts: rockchip: rk3588s-tablet: revert peripheral dr_mode for usbotg0 
Change-Id: I4f9bc2114b13891178154c6cdedbb5c75181ebb3
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
 2021-11-22 16:57:16 +08:00
Ding Wei
dd1bea4b76 video: rockchip: mpp: move session->wait to task->wait 
reason:
1. If the task in the session is assigned to two different cores, the
task in the back may complete first and trigger the wait signal of the
session.
2. In the wait thread, it is taken according to the pending list order,
and the previous task will be triggered, and it must not be found in
the list.
3. For the above reasons, put the wait signal into the task and monitor
the wait signal of the task according to the pending order, then the
order will not be wrong.
4. According to this method, done_list can also be unnecessary.

relative log:
session 000000003edbfbaa task 00000000207419c6, not found in done list!
session 000000003edbfbaa task 000000006a0597ed, not found in done list!
session 000000003edbfbaa task 00000000fe35cb90, not found in done list!
session 000000003edbfbaa task 000000001638cf87, not found in done list!
session 000000003edbfbaa task 00000000a2ba5976, not found in done list!

Change-Id: I2ab6c98162cc4b71ef34cbcda0bc30434fecdb5d
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
 2021-11-22 16:21:11 +08:00
Wyon Bi
eb9ef7a3a0 drm/rockchip: vop2: Fix K value for DP split mode 
K should be 2 for all connector in dual channel mode.
YUV420 output is not supported at dual channel mode.

Change-Id: I03e5147304ad494a3617acc0ba9acafb374088eb
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2021-11-22 16:15:55 +08:00
Zefa Chen
c5bec83187 media: rockchip: rkcif fixed bug of enable dma capture 
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I9fa84cb17a9288ca46c76527e0c9f3f4cb715d53
 2021-11-22 16:08:57 +08:00
Lin Jinhan
6c157a9ba2 crypto: rockchip: move algs private data from rk_crypto_dev 
Algos private data should store in tfm's ctx field to avoid
modify by other algos while calculating.

Change-Id: I1c77e408e3374c697849ec508323131bf5f488b2
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
 2021-11-22 16:05:26 +08:00
Lin Jinhan
a26979bf63 crypto: rockchip: optimize the coding style 
Rename some struct name and variable name been more clearly.

Change-Id: Icf5e6f9d1a7e3f4abfbe05b3fb0034651a120039
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
 2021-11-22 16:05:26 +08:00
Lin Jinhan
2ab2181d46 crypto: rockchip: add rk3568 support 
Change-Id: Ie83dc798cd584d74d9e9b068af17518596ac82dc
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
 2021-11-22 16:05:26 +08:00
Lin Jinhan
31bd563fc7 crypto: rockchip: mask lock_step error int flag 
lock_step will accidentally triggered sometimes.

Change-Id: I401c662d515cf17e6c89dfb2dfa4b33b6866b8a5
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
 2021-11-22 16:05:26 +08:00
Lin Jinhan
e2fb7bc2c3 crypto: rockchip: v2 fix bug calculations stuck when buffer not align 
Data will divide into multi parts to calculating while buffer not
aligned, and crypto BC_CTL/HASH_CTL only be initialized at first
time. Crypto module will be stuck at second calculations if
BC_CTL/HASH_CTL is cleared after every calculations.

Change-Id: I753c4cefbcefcbf38f36f9a6798f406979b4d17d
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
 2021-11-22 16:05:26 +08:00
shengfei Xu
acd264533a regulator: rk806: fix up the regulator_is_enabled return error 
Use rk806_regulator_is_enabled_regmap() to replace regulator_is_enabled_regmap().

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: Ia6aae397ffcbfd7dbd7f45d3defa8544be32e6ad
 2021-11-22 15:52:06 +08:00
shengfei Xu
842c51cac6 regulator: rk806: fix the dcdc/ldo usager counter unbalance 
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: Iea2fe117f9958cbd2a693ea44f477d4d97a555a6
 2021-11-22 15:52:06 +08:00
Zefa Chen
9372704d34 arm64: dts: rockchip: rk3588: modify mipi dcphy address for rx/tx 
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Id4f5a818bcdd0342701c6ff281b8c90fbf31e52f
 2021-11-22 15:05:51 +08:00